Skip to content

Commit 2daf066

Browse files
samples/tests: adc: silabs: add multiple device overlays.
This commit introduces/updates overlays for multiple silabs boards for ADC samples and ADC tests. Signed-off-by: Martin Hoff <[email protected]>
1 parent e4e683a commit 2daf066

29 files changed

+1090
-23
lines changed
Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,37 @@
1+
/*
2+
* Copyright (c) 2025 Silicon Laboratories Inc.
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
#include "dt-bindings/adc/silabs-adc.h"
8+
9+
/ {
10+
zephyr,user {
11+
io-channels = <&adc0 0>, <&adc0 1>;
12+
};
13+
};
14+
15+
&adc0 {
16+
status = "okay";
17+
#address-cells = <1>;
18+
#size-cells = <0>;
19+
20+
channel@0 {
21+
reg = <0>;
22+
zephyr,gain = "ADC_GAIN_1";
23+
zephyr,reference = "ADC_REF_INTERNAL";
24+
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
25+
zephyr,resolution = <12>;
26+
zephyr,input-positive = <IADC_INPUT_IOVDD>;
27+
};
28+
29+
channel@1 {
30+
reg = <1>;
31+
zephyr,gain = "ADC_GAIN_1";
32+
zephyr,reference = "ADC_REF_INTERNAL";
33+
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
34+
zephyr,resolution = <12>;
35+
zephyr,input-positive = <IADC_INPUT_VBAT>;
36+
};
37+
};
Lines changed: 49 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,49 @@
1+
/*
2+
* SPDX-License-Identifier: Apache-2.0
3+
*
4+
* Copyright (c) 2025 Silicon Laboratories Inc.
5+
*/
6+
7+
#include <dt-bindings/adc/silabs-adc.h>
8+
9+
/ {
10+
zephyr,user {
11+
io-channels = <&adc0 3>, <&adc0 4>;
12+
};
13+
};
14+
15+
&pinctrl {
16+
adc0_default: adc0_default {
17+
group0 {
18+
/* Allocate odd bus 0 on GPIO port B to IADC for access to pin PB1 */
19+
silabs,analog-bus = <ABUS_BODD0_IADC0>;
20+
};
21+
};
22+
};
23+
24+
&adc0 {
25+
pinctrl-0 = <&adc0_default>;
26+
pinctrl-names = "default";
27+
#address-cells = <1>;
28+
#size-cells = <0>;
29+
status = "okay";
30+
31+
channel@3 {
32+
reg = <3>;
33+
zephyr,gain = "ADC_GAIN_1";
34+
zephyr,reference = "ADC_REF_INTERNAL";
35+
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
36+
zephyr,resolution = <12>;
37+
zephyr,input-positive = <IADC_INPUT_AVDD>;
38+
};
39+
40+
channel@4 {
41+
reg = <4>;
42+
zephyr,gain = "ADC_GAIN_1";
43+
zephyr,reference = "ADC_REF_VDD_1";
44+
zephyr,vref-mv = <3000>;
45+
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
46+
zephyr,resolution = <12>;
47+
zephyr,input-positive = <IADC_INPUT_PB3>;
48+
};
49+
};
Lines changed: 50 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,50 @@
1+
/*
2+
* SPDX-License-Identifier: Apache-2.0
3+
*
4+
* Copyright (c) 2025 Silicon Laboratories Inc.
5+
*/
6+
7+
#include <dt-bindings/adc/silabs-adc.h>
8+
9+
/ {
10+
zephyr,user {
11+
io-channels = <&adc0 3>, <&adc0 4>;
12+
};
13+
};
14+
15+
&pinctrl {
16+
adc0_default: adc0_default {
17+
group0 {
18+
/* Allocate odd bus 0 on GPIO port C/D to IADC for access to pin PD3 */
19+
silabs,analog-bus = <ABUS_CDODD0_IADC0>;
20+
};
21+
};
22+
};
23+
24+
&adc0 {
25+
pinctrl-0 = <&adc0_default>;
26+
pinctrl-names = "default";
27+
#address-cells = <1>;
28+
#size-cells = <0>;
29+
status = "okay";
30+
31+
channel@3 {
32+
reg = <3>;
33+
zephyr,gain = "ADC_GAIN_1";
34+
zephyr,reference = "ADC_REF_INTERNAL";
35+
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
36+
zephyr,resolution = <12>;
37+
zephyr,input-positive = <IADC_INPUT_AVDD>;
38+
};
39+
40+
channel@4 {
41+
reg = <4>;
42+
zephyr,gain = "ADC_GAIN_1";
43+
zephyr,reference = "ADC_REF_VDD_1";
44+
zephyr,vref-mv = <3300>;
45+
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
46+
zephyr,resolution = <12>;
47+
zephyr,input-positive = <IADC_INPUT_PD3>;
48+
};
49+
50+
};
Lines changed: 68 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,68 @@
1+
/*
2+
* SPDX-License-Identifier: Apache-2.0
3+
*
4+
* Copyright (c) 2025 Silicon Laboratories Inc.
5+
*/
6+
7+
#include <dt-bindings/adc/silabs-adc.h>
8+
9+
/ {
10+
zephyr,user {
11+
io-channels = <&adc0 3>, <&adc0 4>, <&adc0 12>;
12+
};
13+
};
14+
15+
&pinctrl {
16+
adc0_default: adc0_default {
17+
group0 {
18+
/* Allocate odd Analog bus 0 on GPIO port B to IADC
19+
* for access to pin PB3.
20+
* Allocate odd Analog bus 1 on GPIO port A to IADC
21+
* for access to pin PA7.
22+
* Allocate even Analog bus 0 on GPIO port C/D to IADC
23+
* for access to pin PD2.
24+
*/
25+
silabs,analog-bus = <ABUS_BODD0_IADC0>,
26+
<ABUS_AODD1_IADC0>,
27+
<ABUS_CDEVEN0_IADC0>;
28+
};
29+
};
30+
};
31+
32+
&adc0 {
33+
pinctrl-0 = <&adc0_default>;
34+
pinctrl-names = "default";
35+
#address-cells = <1>;
36+
#size-cells = <0>;
37+
status = "okay";
38+
39+
channel@3 {
40+
reg = <3>;
41+
zephyr,gain = "ADC_GAIN_1";
42+
zephyr,reference = "ADC_REF_INTERNAL";
43+
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
44+
zephyr,resolution = <12>;
45+
zephyr,input-positive = <IADC_INPUT_AVDD>;
46+
};
47+
48+
channel@4 {
49+
reg = <4>;
50+
zephyr,gain = "ADC_GAIN_1";
51+
zephyr,reference = "ADC_REF_VDD_1";
52+
zephyr,vref-mv = <3300>;
53+
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
54+
zephyr,resolution = <12>;
55+
zephyr,input-positive = <IADC_INPUT_PB3>;
56+
};
57+
58+
channel@c {
59+
reg = <12>;
60+
zephyr,gain = "ADC_GAIN_1";
61+
zephyr,reference = "ADC_REF_VDD_1";
62+
zephyr,vref-mv = <3300>;
63+
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
64+
zephyr,resolution = <12>;
65+
zephyr,input-positive = <IADC_INPUT_PA7>; /* WPK EXP HEADER 13 */
66+
zephyr,input-negative = <IADC_INPUT_PD2>; /* WPK EXP HEADER 9 */
67+
};
68+
};

samples/drivers/adc/adc_dt/boards/xg24_rb4187c.overlay

Lines changed: 18 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4,20 +4,23 @@
44
* Copyright (c) 2025 Silicon Laboratories Inc.
55
*/
66

7-
#include <dt-bindings/pinctrl/silabs/xg24-pinctrl.h>
87
#include <dt-bindings/adc/silabs-adc.h>
98

109
/ {
1110
zephyr,user {
12-
io-channels = <&adc0 3>, <&adc0 4>;
11+
io-channels = <&adc0 3>, <&adc0 4>, <&adc0 12>;
1312
};
1413
};
1514

1615
&pinctrl {
1716
adc0_default: adc0_default {
1817
group0 {
19-
/* Allocate odd bus 0 on GPIO port B to IADC for access to pin PB1 */
20-
silabs,analog-bus = <ABUS_BODD0_IADC0>;
18+
/* Allocate odd Analog bus 0 on GPIO port B to IADC
19+
* for access to pin PB2 and PB5.
20+
* Allocate even Analog bus 0 on GPIO port C/D to IADC
21+
* for access to pin PC0.
22+
*/
23+
silabs,analog-bus = <ABUS_BODD0_IADC0>, <ABUS_CDEVEN0_IADC0>;
2124
};
2225
};
2326
};
@@ -47,4 +50,15 @@
4750
zephyr,resolution = <12>;
4851
zephyr,input-positive = <IADC_INPUT_PB1>;
4952
};
53+
54+
channel@c {
55+
reg = <12>;
56+
zephyr,gain = "ADC_GAIN_1";
57+
zephyr,reference = "ADC_REF_VDD_1";
58+
zephyr,vref-mv = <3300>;
59+
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
60+
zephyr,resolution = <12>;
61+
zephyr,input-positive = <IADC_INPUT_PB5>; /* WPK EXP HEADER 3 */
62+
zephyr,input-negative = <IADC_INPUT_PC0>; /* WPK EXP HEADER 10 */
63+
};
5064
};
Lines changed: 49 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,49 @@
1+
/*
2+
* SPDX-License-Identifier: Apache-2.0
3+
*
4+
* Copyright (c) 2025 Silicon Laboratories Inc.
5+
*/
6+
7+
#include <dt-bindings/adc/silabs-adc.h>
8+
9+
/ {
10+
zephyr,user {
11+
io-channels = <&adc0 3>, <&adc0 4>;
12+
};
13+
};
14+
15+
&pinctrl {
16+
adc0_default: adc0_default {
17+
group0 {
18+
/* Allocate odd bus 0 on GPIO port B to IADC for access to pin PB1 */
19+
silabs,analog-bus = <ABUS_BODD0_IADC0>;
20+
};
21+
};
22+
};
23+
24+
&adc0 {
25+
pinctrl-0 = <&adc0_default>;
26+
pinctrl-names = "default";
27+
#address-cells = <1>;
28+
#size-cells = <0>;
29+
status = "okay";
30+
31+
channel@3 {
32+
reg = <3>;
33+
zephyr,gain = "ADC_GAIN_1";
34+
zephyr,reference = "ADC_REF_INTERNAL";
35+
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
36+
zephyr,resolution = <12>;
37+
zephyr,input-positive = <IADC_INPUT_AVDD>;
38+
};
39+
40+
channel@4 {
41+
reg = <4>;
42+
zephyr,gain = "ADC_GAIN_1";
43+
zephyr,reference = "ADC_REF_VDD_1";
44+
zephyr,vref-mv = <3300>;
45+
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
46+
zephyr,resolution = <12>;
47+
zephyr,input-positive = <IADC_INPUT_PB3>;
48+
};
49+
};

samples/drivers/adc/adc_dt/boards/xg29_rb4412a.overlay

Lines changed: 21 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -16,8 +16,12 @@
1616
&pinctrl {
1717
adc0_default: adc0_default {
1818
group0 {
19-
/* Allocate odd bus 0 on GPIO port C/D to IADC for access to pin PD3 */
20-
silabs,analog-bus = <ABUS_CDODD0_IADC0>;
19+
/* Allocate odd Analog bus 0 on GPIO port C/D to IADC
20+
* for access to pin PD3 and PC3.
21+
* Allocate even Analog bus 0 on GPIO port A to IADC
22+
* for access to pin PA8.
23+
*/
24+
silabs,analog-bus = <ABUS_CDODD0_IADC0>, <ABUS_AEVEN0_IADC0>;
2125
};
2226
};
2327
};
@@ -34,7 +38,8 @@
3438
zephyr,gain = "ADC_GAIN_1";
3539
zephyr,reference = "ADC_REF_INTERNAL";
3640
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
37-
zephyr,resolution = <12>;
41+
zephyr,oversampling = <5>;
42+
zephyr,resolution = <16>;
3843
zephyr,input-positive = <IADC_INPUT_AVDD>;
3944
};
4045

@@ -44,7 +49,20 @@
4449
zephyr,reference = "ADC_REF_VDD_1";
4550
zephyr,vref-mv = <3300>;
4651
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
52+
zephyr,oversampling = <5>;
4753
zephyr,resolution = <12>;
4854
zephyr,input-positive = <IADC_INPUT_PD3>;
4955
};
56+
57+
channel@c {
58+
reg = <12>;
59+
zephyr,gain = "ADC_GAIN_1";
60+
zephyr,reference = "ADC_REF_VDD_1";
61+
zephyr,vref-mv = <3300>;
62+
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
63+
zephyr,oversampling = <5>;
64+
zephyr,resolution = <16>;
65+
zephyr,input-positive = <IADC_INPUT_PC3>; /* WPK EXP HEADER 10 */
66+
zephyr,input-negative = <IADC_INPUT_PA8>; /* WPK EXP HEADER 13 */
67+
};
5068
};

samples/drivers/adc/adc_dt/sample.yaml

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -37,8 +37,13 @@ tests:
3737
- mcx_n9xx_evk/mcxn947/cpu0
3838
- frdm_mcxc242
3939
- ucans32k1sic
40+
- sltb010a
41+
- slwrb4180a
42+
- xg23_rb4210a
4043
- xg24_rb4187c
44+
- xg27_dk2602a
4145
- xg29_rb4412a
46+
- bg29_rb4420a
4247
- raytac_an54l15q_db/nrf54l15/cpuapp
4348
- frdm_mcxa346
4449
- frdm_mcxa266

0 commit comments

Comments
 (0)