dts: arm: introduce gd32 spi interface

Add gd32 spi initial support.

Signed-off-by: HaiLong Yang <[email protected]>

Author: cameled

dts/arm/gigadevice/gd32f403/gd32f403.dtsi

@@ -95,6 +95,39 @@
 			label = "USART_4";
 		};
 
+		spi0: spi@40013000 {
+			compatible = "gd,gd32-spi";
+			reg = <0x40013000 0x400>;
+			interrupts = <35 0>;
+			rcu-periph-clock = <0x60c>;
+			status = "disabled";
+			label = "SPI_0";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		spi1: spi@40003800 {
+			compatible = "gd,gd32-spi";
+			reg = <0x40003800 0x400>;
+			interrupts = <36 0>;
+			rcu-periph-clock = <0x70e>;
+			status = "disabled";
+			label = "SPI_1";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		spi2: spi@40003c00 {
+			compatible = "gd,gd32-spi";
+			reg = <0x40003c00 0x400>;
+			interrupts = <51 0>;
+			rcu-periph-clock = <0x70f>;
+			status = "disabled";
+			label = "SPI_2";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		exti: interrupt-controller@40010400 {
 			compatible = "gd,gd32-exti";
 			interrupt-controller;

dts/arm/gigadevice/gd32f4xx/gd32f450.dtsi

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2021 BrainCo Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <gigadevice/gd32f4xx/gd32f4xx.dtsi>
+
+/ {
+	soc {
+		spi3: spi@40013400 {
+			compatible = "gd,gd32-spi";
+			reg = <0x40013400 0x400>;
+			interrupts = <84 0>;
+			rcu-periph-clock = <0x110d>;
+			status = "disabled";
+			label = "SPI_3";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		spi4: spi@40015000 {
+			compatible = "gd,gd32-spi";
+			reg = <0x40015000 0x400>;
+			interrupts = <85 0>;
+			rcu-periph-clock = <0x1114>;
+			status = "disabled";
+			label = "SPI_4";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		spi5: spi@40015400 {
+			compatible = "gd,gd32-spi";
+			reg = <0x40015400 0x400>;
+			interrupts = <86 0>;
+			rcu-periph-clock = <0x1115>;
+			status = "disabled";
+			label = "SPI_5";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+	};
+};

dts/arm/gigadevice/gd32f4xx/gd32f450ik.dtsi

@@ -5,7 +5,7 @@
  */
 
 #include <mem.h>
-#include <gigadevice/gd32f4xx/gd32f4xx.dtsi>
+#include <gigadevice/gd32f4xx/gd32f450.dtsi>
 
 / {
 	soc {

dts/arm/gigadevice/gd32f4xx/gd32f4xx.dtsi

@@ -171,6 +171,39 @@
 			label = "I2C_2";
 		};
 
+		spi0: spi@40013000 {
+			compatible = "gd,gd32-spi";
+			reg = <0x40013000 0x400>;
+			interrupts = <35 0>;
+			rcu-periph-clock = <0x110c>;
+			status = "disabled";
+			label = "SPI_0";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		spi1: spi@40003800 {
+			compatible = "gd,gd32-spi";
+			reg = <0x40003800 0x400>;
+			interrupts = <36 0>;
+			rcu-periph-clock = <0x100e>;
+			status = "disabled";
+			label = "SPI_1";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		spi2: spi@40003c00 {
+			compatible = "gd,gd32-spi";
+			reg = <0x40003c00 0x400>;
+			interrupts = <51 0>;
+			rcu-periph-clock = <0x100f>;
+			status = "disabled";
+			label = "SPI_2";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		syscfg: syscfg@40013800 {
 			compatible = "gd,gd32-syscfg";
 			reg = <0x40013800 0x400>;

dts/bindings/spi/gd,gd32-spi.yaml

@@ -0,0 +1,26 @@
+# Copyright (c) 2021 BrainCo Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: GigaDevice GD32 SPI
+
+compatible: "gd,gd32-spi"
+
+include: [spi-controller.yaml, pinctrl-device.yaml]
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  rcu-periph-clock:
+    type: int
+    description: Peripheral RCU(Reset Clock Unit) Clock ID
+    required: true
+
+  pinctrl-0:
+    required: true
+
+  pinctrl-names:
+    required: true

dts/riscv/gigadevice/gd32vf103.dtsi

@@ -123,6 +123,18 @@
 			label = "I2C_0";
 		};
 
+		spi0: spi@40013000 {
+			compatible = "gd,gd32-spi";
+			reg = <0x40013000 0x400>;
+			interrupts = <54 0>;
+			interrupt-parent = <&eclic>;
+			rcu-periph-clock = <0x60c>;
+			status = "disabled";
+			label = "SPI_0";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		afio: afio@40010000 {
 			compatible = "gd,gd32-afio";
 			reg = <0x40010000 0x400>;