drivers: flash: flexspi_mx25um51345g: fix DDR dummy cycles

In the DDR LUT, the dummy cycles were not defined for READ_STATUS_REG
and had a wrong value for READ.
The default amount of dummy cycles on this chip are 20 (0x14).
This means the LUT should contain the value of 0x28 (0x14*2) for DDR
at these entries.

Signed-off-by: Andre Heinemans <[email protected]>

Author: AndreHeinemans-NXP

drivers/flash/flash_mcux_flexspi_mx25um51345g.c

@@ -105,6 +105,7 @@ static const uint32_t flash_flexspi_nor_lut[][4] = {
 		FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR,	kFLEXSPI_8PAD, 0x04,
 				kFLEXSPI_Command_STOP,		kFLEXSPI_1PAD, 0x0),
 	},
+
 	[WRITE_ENABLE_OPI] = {
 		FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR,		kFLEXSPI_8PAD, 0x06,
 				kFLEXSPI_Command_SDR,		kFLEXSPI_8PAD, 0xF9),
@@ -142,7 +143,9 @@ static const uint32_t flash_flexspi_nor_lut[][4] = {
 		FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR,		kFLEXSPI_8PAD, 0x05,
 				kFLEXSPI_Command_DDR,		kFLEXSPI_8PAD, 0xFA),
 		FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR,	kFLEXSPI_8PAD, 0x20,
-				kFLEXSPI_Command_READ_DDR,	kFLEXSPI_8PAD, 0x4),
+				kFLEXSPI_Command_DUMMY_DDR,	kFLEXSPI_8PAD, 0x28),
+		FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR,	kFLEXSPI_8PAD, 0x4,
+				kFLEXSPI_Command_STOP,		kFLEXSPI_1PAD, 0x0),
 	},
 
 	[WRITE_ENABLE_OPI] = {
@@ -166,7 +169,7 @@ static const uint32_t flash_flexspi_nor_lut[][4] = {
 		FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DDR,		kFLEXSPI_8PAD, 0xEE,
 				kFLEXSPI_Command_DDR,		kFLEXSPI_8PAD, 0x11),
 		FLEXSPI_LUT_SEQ(kFLEXSPI_Command_RADDR_DDR,	kFLEXSPI_8PAD, 0x20,
-				kFLEXSPI_Command_DUMMY_DDR,	kFLEXSPI_8PAD, 0x08),
+				kFLEXSPI_Command_DUMMY_DDR,	kFLEXSPI_8PAD, 0x28),
 		FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_DDR,	kFLEXSPI_8PAD, 0x04,
 				kFLEXSPI_Command_STOP,		kFLEXSPI_1PAD, 0x0),
 	},