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| 1 | +/* |
| 2 | + * Copyright (c) 2019 Linaro Limited |
| 3 | + * |
| 4 | + * SPDX-License-Identifier: Apache-2.0 |
| 5 | + */ |
| 6 | + |
| 7 | +#define LOG_DOMAIN flash_stm32wb |
| 8 | +#define LOG_LEVEL CONFIG_FLASH_LOG_LEVEL |
| 9 | +#include <logging/log.h> |
| 10 | +LOG_MODULE_REGISTER(LOG_DOMAIN); |
| 11 | + |
| 12 | +#include <kernel.h> |
| 13 | +#include <device.h> |
| 14 | +#include <string.h> |
| 15 | +#include <flash.h> |
| 16 | +#include <init.h> |
| 17 | +#include <soc.h> |
| 18 | +#include <misc/__assert.h> |
| 19 | + |
| 20 | +#include "flash_stm32.h" |
| 21 | + |
| 22 | +#define STM32WBX_PAGE_SHIFT 12 |
| 23 | + |
| 24 | +/* offset and len must be aligned on 8 for write, |
| 25 | + * positive and not beyond end of flash |
| 26 | + */ |
| 27 | +bool flash_stm32_valid_range(struct device *dev, off_t offset, u32_t len, |
| 28 | + bool write) |
| 29 | +{ |
| 30 | + return (!write || (offset % 8 == 0 && len % 8 == 0U)) && |
| 31 | + flash_stm32_range_exists(dev, offset, len); |
| 32 | +} |
| 33 | + |
| 34 | +/* |
| 35 | + * Up to 255 4K pages |
| 36 | + */ |
| 37 | +static u32_t get_page(off_t offset) |
| 38 | +{ |
| 39 | + return offset >> STM32WBX_PAGE_SHIFT; |
| 40 | +} |
| 41 | + |
| 42 | +static int write_dword(struct device *dev, off_t offset, u64_t val) |
| 43 | +{ |
| 44 | + volatile u32_t *flash = (u32_t *)(offset + CONFIG_FLASH_BASE_ADDRESS); |
| 45 | + struct stm32wbx_flash *regs = FLASH_STM32_REGS(dev); |
| 46 | + u32_t tmp; |
| 47 | + int ret, rc; |
| 48 | + |
| 49 | + /* if the control register is locked, do not fail silently */ |
| 50 | + if (regs->cr & FLASH_CR_LOCK) { |
| 51 | + rc = -EIO; |
| 52 | + } |
| 53 | + |
| 54 | + /* Check if this double word is erased */ |
| 55 | + if (flash[0] != 0xFFFFFFFFUL || |
| 56 | + flash[1] != 0xFFFFFFFFUL) { |
| 57 | + return -EIO; |
| 58 | + } |
| 59 | + |
| 60 | + ret = flash_stm32_check_status(dev); |
| 61 | + if (ret < 0) { |
| 62 | + return -EIO; |
| 63 | + } |
| 64 | + |
| 65 | + /* Set the PG bit */ |
| 66 | + regs->cr |= FLASH_CR_PG; |
| 67 | + |
| 68 | + /* Flush the register write */ |
| 69 | + tmp = regs->cr; |
| 70 | + |
| 71 | + /* Perform the data write operation at the desired memory address */ |
| 72 | + flash[0] = (u32_t)val; |
| 73 | + flash[1] = (u32_t)(val >> 32); |
| 74 | + |
| 75 | + /* Wait until the BSY bit is cleared */ |
| 76 | + rc = flash_stm32_wait_flash_idle(dev); |
| 77 | + |
| 78 | + /* Clear the PG bit */ |
| 79 | + regs->cr &= (~FLASH_CR_PG); |
| 80 | + |
| 81 | + return 0; |
| 82 | +} |
| 83 | + |
| 84 | +static int erase_page(struct device *dev, u32_t page) |
| 85 | +{ |
| 86 | + struct stm32wbx_flash *regs = FLASH_STM32_REGS(dev); |
| 87 | + int rc; |
| 88 | + |
| 89 | + /* if the control register is locked, do not fail silently */ |
| 90 | + if (regs->cr & FLASH_CR_LOCK) { |
| 91 | + return -EIO; |
| 92 | + } |
| 93 | + |
| 94 | + /* Check that no Flash memory operation is ongoing */ |
| 95 | + rc = flash_stm32_wait_flash_idle(dev); |
| 96 | + if (rc < 0) { |
| 97 | + return rc; |
| 98 | + } |
| 99 | + |
| 100 | + /* Check erase operation allowed */ |
| 101 | + if (regs->cr & FLASH_SR_PESD) { |
| 102 | + return -EBUSY; |
| 103 | + } |
| 104 | + |
| 105 | + /* Proceed to erase the page */ |
| 106 | + regs->cr |= FLASH_CR_PER; |
| 107 | + regs->cr &= ~FLASH_CR_PNB_Msk; |
| 108 | + regs->cr |= page << FLASH_CR_PNB_Pos; |
| 109 | + |
| 110 | + regs->cr |= FLASH_CR_STRT; |
| 111 | + |
| 112 | + /* Wait for the BSY bit */ |
| 113 | + rc = flash_stm32_wait_flash_idle(dev); |
| 114 | + |
| 115 | + regs->cr &= (~FLASH_TYPEERASE_PAGES); |
| 116 | + |
| 117 | + return rc; |
| 118 | +} |
| 119 | + |
| 120 | +int flash_stm32_block_erase_loop(struct device *dev, unsigned int offset, |
| 121 | + unsigned int len) |
| 122 | +{ |
| 123 | + int i, rc = 0; |
| 124 | + |
| 125 | + i = get_page(offset); |
| 126 | + for (; i <= get_page(offset + len - 1) ; ++i) { |
| 127 | + rc = erase_page(dev, i); |
| 128 | + if (rc < 0) { |
| 129 | + break; |
| 130 | + } |
| 131 | + } |
| 132 | + |
| 133 | + return rc; |
| 134 | +} |
| 135 | + |
| 136 | +int flash_stm32_write_range(struct device *dev, unsigned int offset, |
| 137 | + const void *data, unsigned int len) |
| 138 | +{ |
| 139 | + int i, rc = 0; |
| 140 | + |
| 141 | + for (i = 0; i < len; i += 8, offset += 8U) { |
| 142 | + rc = write_dword(dev, offset, |
| 143 | + UNALIGNED_GET((const u64_t *) data + (i >> 3))); |
| 144 | + if (rc < 0) { |
| 145 | + return rc; |
| 146 | + } |
| 147 | + } |
| 148 | + |
| 149 | + return rc; |
| 150 | +} |
| 151 | + |
| 152 | +void flash_stm32_page_layout(struct device *dev, |
| 153 | + const struct flash_pages_layout **layout, |
| 154 | + size_t *layout_size) |
| 155 | +{ |
| 156 | + static struct flash_pages_layout stm32wb_flash_layout = { |
| 157 | + .pages_count = 0, |
| 158 | + .pages_size = 0, |
| 159 | + }; |
| 160 | + |
| 161 | + ARG_UNUSED(dev); |
| 162 | + |
| 163 | + if (stm32wb_flash_layout.pages_count == 0) { |
| 164 | + stm32wb_flash_layout.pages_count = FLASH_SIZE / FLASH_PAGE_SIZE; |
| 165 | + stm32wb_flash_layout.pages_size = FLASH_PAGE_SIZE; |
| 166 | + } |
| 167 | + |
| 168 | + *layout = &stm32wb_flash_layout; |
| 169 | + *layout_size = 1; |
| 170 | +} |
| 171 | + |
| 172 | +int flash_stm32_check_status(struct device *dev) |
| 173 | +{ |
| 174 | + struct stm32wbx_flash *regs = FLASH_STM32_REGS(dev); |
| 175 | + u32_t error = 0; |
| 176 | + |
| 177 | + /* Save Flash errors */ |
| 178 | + error = (regs->sr & FLASH_FLAG_SR_ERROR); |
| 179 | + error |= (regs->eccr & FLASH_FLAG_ECCC); |
| 180 | + |
| 181 | + /* Clear systematic Option and Enginneering bits validity error */ |
| 182 | + if (error & FLASH_FLAG_OPTVERR) { |
| 183 | + regs->sr |= FLASH_FLAG_SR_ERROR; |
| 184 | + return 0; |
| 185 | + } |
| 186 | + |
| 187 | + if (error) { |
| 188 | + return -EIO; |
| 189 | + } |
| 190 | + |
| 191 | + return 0; |
| 192 | +} |
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