@@ -146,10 +146,14 @@ struct dma_mcux_edma_data {
146146#define EDMA_TCD_CITER (tcd , flag ) ((tcd)->CITER)
147147#define EDMA_TCD_CSR (tcd , flag ) ((tcd)->CSR)
148148#define EDMA_TCD_DLAST_SGA (tcd , flag ) ((tcd)->DLAST_SGA)
149- #define EDMA_HW_TCD_CH_ACTIVE_MASK (DMA_CSR_ACTIVE_MASK)
149+ #ifdef CONFIG_DMA_MCUX_EDMA
150+ #define EDMA_TCD_CSR_DREQ (x ) DMA_CSR_DREQ(x)
151+ #elif defined(CONFIG_DMA_MCUX_EDMA_V3 )
152+ #define EDMA_TCD_CSR_DREQ (x ) DMA_TCD_CSR_DREQ(x)
153+ #endif
150154#elif defined(CONFIG_DMA_MCUX_EDMA_V4 )
151155/* Above macros have been defined in fsl_edma_core.h */
152- #define EDMA_HW_TCD_CH_ACTIVE_MASK (DMA_CH_CSR_ACTIVE_MASK )
156+ #define EDMA_TCD_CSR_DREQ ( x ) DMA_CSR_DREQ(x )
153157#endif
154158
155159/* Definations for HW TCD fields */
@@ -159,12 +163,14 @@ struct dma_mcux_edma_data {
159163#define EDMA_HW_TCD_BITER (dev , ch ) (DEV_BASE(dev)->TCD[ch].BITER_ELINKNO)
160164#define EDMA_HW_TCD_CITER (dev , ch ) (DEV_BASE(dev)->TCD[ch].CITER_ELINKNO)
161165#define EDMA_HW_TCD_CSR (dev , ch ) (DEV_BASE(dev)->TCD[ch].CSR)
166+ #define EDMA_HW_TCD_CH_ACTIVE_MASK (DMA_CSR_ACTIVE_MASK)
162167#elif defined(CONFIG_DMA_MCUX_EDMA_V3 ) || defined(CONFIG_DMA_MCUX_EDMA_V4 )
163168#define EDMA_HW_TCD_SADDR (dev , ch ) (DEV_BASE(dev)->CH[ch].TCD_SADDR)
164169#define EDMA_HW_TCD_DADDR (dev , ch ) (DEV_BASE(dev)->CH[ch].TCD_DADDR)
165170#define EDMA_HW_TCD_BITER (dev , ch ) (DEV_BASE(dev)->CH[ch].TCD_BITER_ELINKNO)
166171#define EDMA_HW_TCD_CITER (dev , ch ) (DEV_BASE(dev)->CH[ch].TCD_CITER_ELINKNO)
167172#define EDMA_HW_TCD_CSR (dev , ch ) (DEV_BASE(dev)->CH[ch].TCD_CSR)
173+ #define EDMA_HW_TCD_CH_ACTIVE_MASK (DMA_CH_CSR_ACTIVE_MASK)
168174#endif
169175
170176/*
@@ -442,9 +448,10 @@ static int dma_mcux_edma_configure(const struct device *dev, uint32_t channel,
442448 block_config -> block_size / config -> source_data_size ;
443449 /*Enable auto stop for last transfer.*/
444450 if (block_config -> next_block == NULL ) {
445- EDMA_TCD_CSR (tcd , kEDMA_EDMA4Flag ) |= DMA_CSR_DREQ (1U );
451+ EDMA_TCD_CSR (tcd , kEDMA_EDMA4Flag ) |= EDMA_TCD_CSR_DREQ (1U );
446452 } else {
447- EDMA_TCD_CSR (tcd , kEDMA_EDMA4Flag ) &= ~DMA_CSR_DREQ (1U );
453+ EDMA_TCD_CSR (tcd , kEDMA_EDMA4Flag ) &=
454+ ~EDMA_TCD_CSR_DREQ (1U );
448455 }
449456
450457 data -> transfer_settings .write_idx =
@@ -604,7 +611,7 @@ static void dma_mcux_edma_update_hw_tcd(const struct device *dev, uint32_t chann
604611 EDMA_HW_TCD_DADDR (dev , channel ) = dst ;
605612 EDMA_HW_TCD_BITER (dev , channel ) = size ;
606613 EDMA_HW_TCD_CITER (dev , channel ) = size ;
607- EDMA_HW_TCD_CSR (dev , channel ) |= DMA_CSR_DREQ (1U );
614+ EDMA_HW_TCD_CSR (dev , channel ) |= EDMA_TCD_CSR_DREQ (1U );
608615}
609616
610617static int dma_mcux_edma_reload (const struct device * dev , uint32_t channel ,
@@ -645,7 +652,7 @@ static int dma_mcux_edma_reload(const struct device *dev, uint32_t channel,
645652 EDMA_TCD_BITER (tcd , kEDMA_EDMA4Flag ) = size ;
646653 EDMA_TCD_CITER (tcd , kEDMA_EDMA4Flag ) = size ;
647654 /* Enable automatically stop */
648- EDMA_TCD_CSR (tcd , kEDMA_EDMA4Flag ) |= DMA_CSR_DREQ (1U );
655+ EDMA_TCD_CSR (tcd , kEDMA_EDMA4Flag ) |= EDMA_TCD_CSR_DREQ (1U );
649656 sw_id = EDMA_TCD_DLAST_SGA (tcd , kEDMA_EDMA4Flag );
650657
651658 /* Block the peripheral's hardware request trigger to prevent
@@ -677,7 +684,7 @@ static int dma_mcux_edma_reload(const struct device *dev, uint32_t channel,
677684 /* Previous TCD can automatically start this TCD.
678685 * Enable the peripheral DMA request in the previous TCD
679686 */
680- EDMA_TCD_CSR (pre_tcd , kEDMA_EDMA4Flag ) &= ~DMA_CSR_DREQ (1U );
687+ EDMA_TCD_CSR (pre_tcd , kEDMA_EDMA4Flag ) &= ~EDMA_TCD_CSR_DREQ (1U );
681688
682689 if (data -> transfer_settings .empty_tcds == CONFIG_DMA_TCD_QUEUE_SIZE - 1 ||
683690 hw_id == (uint32_t )tcd ) {
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