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Hieu Nguyen
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soc: renesas: Add support for Renesas RZ/T2L
Add support for Renesas RZ/T2L Signed-off-by: Hieu Nguyen <[email protected]> Signed-off-by: Nhut Nguyen <[email protected]>
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‎dts/arm/renesas/rz/rzt/r9a07g074.dtsi‎

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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <arm/armv8-r.dtsi>
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#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "renesas,r9a07g074";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-r52";
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reg = <0>;
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};
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};
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arch_timer: timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
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interrupt-parent = <&gic>;
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};
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soc {
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interrupt-parent = <&gic>;
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gic: interrupt-controller@94000000 {
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compatible = "arm,gic-v3", "arm,gic";
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reg = <0x94000000 0x10000>,
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<0x94100000 0x80000>;
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interrupt-controller;
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#interrupt-cells = <4>;
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status = "okay";
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};
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atcm: memory@0 {
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compatible = "mmio-sram";
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reg = <0x00000000 DT_SIZE_K(512)>;
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};
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btcm: memory@100000 {
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compatible = "mmio-sram";
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reg = <0x00100000 DT_SIZE_K(64)>;
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};
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sram: memory@10000000 {
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compatible = "mmio-sram";
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reg = <0x10000000 DT_SIZE_M(1)>;
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};
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xspi1_cs0: memory@68000000 {
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compatible = "mmio-sram";
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reg = <0x68000000 DT_SIZE_M(16)>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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loader_param: partition@0 {
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label = "loader-param";
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reg = <0x00000000 0x4C>;
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read-only;
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};
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loader_program: partition@4C {
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label = "loader-program";
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reg = <0x0000004C (DT_SIZE_K(56) - 0x4C)>;
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read-only;
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};
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slot0_partition: partition@E000 {
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label = "image-0";
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reg = <0x0000E000 (DT_SIZE_M(16) - DT_SIZE_K(56))>;
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read-only;
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};
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};
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};
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};
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};

‎soc/renesas/rz/rzt2l/CMakeLists.txt‎

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# Copyright (c) 2025 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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zephyr_sources(
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soc.c
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loader_param.c
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../common/loader_program.S
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)
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zephyr_include_directories(.)
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zephyr_linker_sources(SECTIONS sections.ld)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_r/scripts/linker.ld CACHE INTERNAL "")

‎soc/renesas/rz/rzt2l/Kconfig‎

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# Copyright (c) 2025 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_RZT2L
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select ARM
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select CPU_CORTEX_R52
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select CPU_HAS_ARM_MPU
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select GIC_SINGLE_SECURITY_STATE
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select ARM_ARCH_TIMER
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select HAS_RENESAS_RZ_FSP
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select SOC_RESET_HOOK
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select SOC_EARLY_INIT_HOOK
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select ARM_CUSTOM_INTERRUPT_CONTROLLER

‎soc/renesas/rz/rzt2l/Kconfig.defconfig‎

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# Copyright (c) 2025 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_RZT2L
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config NUM_IRQS
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default 480
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 25000000
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config FPU
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default y
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config FLASH_SIZE
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default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
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config FLASH_BASE_ADDRESS
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default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
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DT_CHOSEN_IMAGE_ZEPHYR = zephyr,code-partition
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config BUILD_OUTPUT_ADJUST_LMA
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default "($(dt_chosen_reg_addr_hex,$(DT_CHOSEN_IMAGE_ZEPHYR)) + \
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$(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)))"
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config BUILD_OUTPUT_ADJUST_LMA_SECTIONS
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default "*;!.loader"
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endif # SOC_SERIES_RZT2L

‎soc/renesas/rz/rzt2l/Kconfig.soc‎

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# Copyright (c) 2025 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_RZT2L
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bool
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select SOC_FAMILY_RENESAS_RZ
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help
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Renesas RZ/T2L series
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config SOC_SERIES
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default "rzt2l" if SOC_SERIES_RZT2L
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config SOC_R9A07G074M04GBG
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bool
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select SOC_SERIES_RZT2L
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help
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R9A07G074M04GBG
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config SOC
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default "r9a07g074m04gbg" if SOC_R9A07G074M04GBG

‎soc/renesas/rz/rzt2l/loader_param.c‎

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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <zephyr/linker/section_tags.h>
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#define CACHE_FLG (0x00000000)
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#define CS0BCR_V_WRAPCFG_V (0x00000000)
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#define CS0WCR_V_COMCFG_V (0x00000000)
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#define DUMMY0_BMCFG_V (0x00000000)
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#define BSC_FLG_xSPI_FLG (0x00000000)
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#define LDR_ADDR_NML (0x6800004C)
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#define LDR_SIZE_NML (0x00006000)
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#define DEST_ADDR_NML (0x00102000)
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#define DUMMY1 (0x00000000)
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#define DUMMY2 (0x00000000)
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#define DUMMY3_CSSCTL_V (0x0000003F)
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#define DUMMY4_LIOCFGCS0_V (0x00070000)
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#define DUMMY5 (0x00000000)
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#define DUMMY6 (0x00000000)
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#define DUMMY7 (0x00000000)
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#define DUMMY8 (0x00000000)
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#define DUMMY9 (0x00000000)
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#define DUMMY10_ACCESS_SPEED (0x00000600)
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#define CHECK_SUM (0xEEA2)
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#define LOADER_PARAM_MAX (19)
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#define __loader_param Z_GENERIC_SECTION(.loader_param)
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const uint32_t loader_param[LOADER_PARAM_MAX] __loader_param = {
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CACHE_FLG,
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CS0BCR_V_WRAPCFG_V,
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CS0WCR_V_COMCFG_V,
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DUMMY0_BMCFG_V,
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BSC_FLG_xSPI_FLG,
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LDR_ADDR_NML,
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LDR_SIZE_NML,
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DEST_ADDR_NML,
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DUMMY1,
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DUMMY2,
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DUMMY3_CSSCTL_V,
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DUMMY4_LIOCFGCS0_V,
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DUMMY5,
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DUMMY6,
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DUMMY7,
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DUMMY8,
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DUMMY9,
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DUMMY10_ACCESS_SPEED,
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CHECK_SUM,
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};

‎soc/renesas/rz/rzt2l/pinctrl_soc.h‎

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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SOC_RENESAS_RZ_RZT2L_PINCTRL_SOC_H_
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#define ZEPHYR_SOC_RENESAS_RZ_RZT2L_PINCTRL_SOC_H_
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#include <pinctrl_rzt.h>
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#endif /* ZEPHYR_SOC_RENESAS_RZ_RZT2L_PINCTRL_SOC_H_ */

‎soc/renesas/rz/rzt2l/sections.ld‎

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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/devicetree.h>
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SECTION_PROLOGUE(.loader, CONFIG_FLASH_BASE_ADDRESS,)
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{
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__loader_param_start = .;
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KEEP(*(.loader_param))
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__loader_param_end = .;
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. = DT_REG_ADDR(DT_NODELABEL(loader_program));
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__loader_program_start = .;
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KEEP(*(.loader_text.*))
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__loader_program_end = .;
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} GROUP_LINK_IN(FLASH)

‎soc/renesas/rz/rzt2l/soc.c‎

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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <bsp_api.h>
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#include <zephyr/init.h>
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#include <zephyr/sys/barrier.h>
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#include <zephyr/drivers/interrupt_controller/gic.h>
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#include <zephyr/irq.h>
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extern void bsp_global_system_counter_init(void);
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void *gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES + BSP_CORTEX_VECTOR_TABLE_ENTRIES];
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IRQn_Type g_current_interrupt_num[32];
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uint8_t g_current_interrupt_pointer;
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void soc_reset_hook(void)
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{
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/* Enable peripheral port access at EL1 and EL0 */
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__asm__ volatile("mrc p15, 0, r0, c15, c0, 0\n");
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__asm__ volatile("orr r0, #1\n");
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__asm__ volatile("mcr p15, 0, r0, c15, c0, 0\n");
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barrier_dsync_fence_full();
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barrier_isync_fence_full();
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}
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void soc_early_init_hook(void)
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{
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/* Configure system clocks. */
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bsp_clock_init();
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/* Initialize SystemCoreClock variable. */
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SystemCoreClockUpdate();
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/* Initialize global system counter. The counter is enabled and is incrementing. */
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bsp_global_system_counter_init();
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}
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unsigned int z_soc_irq_get_active(void)
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{
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int intid = arm_gic_get_active();
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g_current_interrupt_num[g_current_interrupt_pointer++] = intid;
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return intid;
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}
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void z_soc_irq_eoi(unsigned int intid)
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{
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g_current_interrupt_pointer--;
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arm_gic_eoi(intid);
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}
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void z_soc_irq_enable(unsigned int irq)
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{
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arm_gic_irq_enable(irq);
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}
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void z_soc_irq_disable(unsigned int irq)
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{
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arm_gic_irq_disable(irq);
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}
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int z_soc_irq_is_enabled(unsigned int irq)
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{
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return arm_gic_irq_is_enabled(irq);
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}
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void z_soc_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
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{
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arm_gic_irq_set_priority(irq, prio, flags);
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}
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void z_soc_irq_init(void)
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{
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g_current_interrupt_pointer = 0;
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}
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/* Porting FSP IRQ configuration by an empty function */
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/* Let Zephyr handle IRQ configuration */
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void bsp_irq_core_cfg(void)
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{
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/* Do nothing */
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}

‎soc/renesas/rz/rzt2l/soc.h‎

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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SOC_RENESAS_RZT2L_SOC_H_
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#define ZEPHYR_SOC_RENESAS_RZT2L_SOC_H_
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typedef enum IRQn {
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SoftwareGeneratedInt0 = 0,
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SoftwareGeneratedInt1,
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SoftwareGeneratedInt2,
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SoftwareGeneratedInt3,
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SoftwareGeneratedInt4,
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SoftwareGeneratedInt5,
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SoftwareGeneratedInt6,
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SoftwareGeneratedInt7,
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SoftwareGeneratedInt8,
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SoftwareGeneratedInt9,
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SoftwareGeneratedInt10,
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SoftwareGeneratedInt11,
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SoftwareGeneratedInt12,
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SoftwareGeneratedInt13,
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SoftwareGeneratedInt14,
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SoftwareGeneratedInt15,
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DebugCommunicationsChannelInt = 22,
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PerformanceMonitorCounterOverflowInt = 23,
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CrossTriggerInterfaceInt = 24,
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VritualCPUInterfaceMaintenanceInt = 25,
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HypervisorTimerInt = 26,
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VirtualTimerInt = 27,
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NonSecurePhysicalTimerInt = 30,
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SHARED_PERIPHERAL_INTERRUPTS_MAX_ENTRIES = CONFIG_NUM_IRQS
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} IRQn_Type;
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/* Do not let CMSIS to handle GIC and Timer */
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#define __GIC_PRESENT 0
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#define __TIM_PRESENT 0
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#define __FPU_PRESENT 1
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/* Porting FSP IRQ configuration by an empty function */
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/* Let Zephyr handle IRQ configuration */
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void bsp_irq_core_cfg(void);
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#endif /* ZEPHYR_SOC_RENESAS_RZT2L_SOC_H_ */

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