Skip to content

Commit 32bf51b

Browse files
hfakkiznashif
authored andcommitted
dts: arm: adi: Add MAX32662 DMA instance and binding file
Add DMA0 node to MAX32662 dtsi file and add binding file for DMA slots. Signed-off-by: Furkan Akkiz <[email protected]>
1 parent 2f314a1 commit 32bf51b

File tree

2 files changed

+40
-0
lines changed

2 files changed

+40
-0
lines changed

dts/arm/adi/max32/max32662.dtsi

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@
66

77
#include <arm/armv7-m.dtsi>
88
#include <adi/max32/max32xxx.dtsi>
9+
#include <zephyr/dt-bindings/dma/max32662_dma.h>
910

1011
&flash0 {
1112
reg = <0x10000000 DT_SIZE_K(256)>;
@@ -59,6 +60,16 @@
5960
reg = <0x20013000 DT_SIZE_K(4)>;
6061
};
6162

63+
dma0: dma@40028000 {
64+
compatible = "adi,max32-dma";
65+
reg = <0x40028000 0x1000>;
66+
clocks = <&gcr ADI_MAX32_CLOCK_BUS0 5>;
67+
interrupts = <28 0>, <29 0>, <30 0>, <31 0>;
68+
dma-channels = <4>;
69+
status = "disabled";
70+
#dma-cells = <2>;
71+
};
72+
6273
spi0: spi@40046000 {
6374
compatible = "adi,max32-spi";
6475
reg = <0x40046000 0x1000>;
Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,29 @@
1+
/*
2+
* Copyright (c) 2024 Analog Devices, Inc.
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32662_DMA_H_
8+
#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32662_DMA_H_
9+
10+
#define MAX32_DMA_SLOT_MEMTOMEM 0x00U
11+
#define MAX32_DMA_SLOT_SPI0_RX 0x01U
12+
#define MAX32_DMA_SLOT_SPI1_RX 0x02U
13+
#define MAX32_DMA_SLOT_UART0_RX 0x04U
14+
#define MAX32_DMA_SLOT_UART1_RX 0x05U
15+
#define MAX32_DMA_SLOT_CAN_RX 0x06U
16+
#define MAX32_DMA_SLOT_I2C0_RX 0x07U
17+
#define MAX32_DMA_SLOT_I2C1_RX 0x08U
18+
#define MAX32_DMA_SLOT_ADC 0x09U
19+
#define MAX32_DMA_SLOT_I2S_RX 0x1EU
20+
#define MAX32_DMA_SLOT_SPI0_TX 0x21U
21+
#define MAX32_DMA_SLOT_SPI1_TX 0x22U
22+
#define MAX32_DMA_SLOT_UART0_TX 0x24U
23+
#define MAX32_DMA_SLOT_UART1_TX 0x25U
24+
#define MAX32_DMA_SLOT_CAN_TX 0x26U
25+
#define MAX32_DMA_SLOT_I2C0_TX 0x27U
26+
#define MAX32_DMA_SLOT_I2C1_TX 0x28U
27+
#define MAX32_DMA_SLOT_I2S_TX 0x3EU
28+
29+
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32662_DMA_H_ */

0 commit comments

Comments
 (0)