tests/drivers/clock_control: stm32h7_device: Add test for CKPER source

Add 2 scenarios to test CKPER used as a clock source.

Signed-off-by: Erwan Gouriou <[email protected]>

Author: erwango

tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/spi1_per_ck_d1ppre_1.overlay

@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2021 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Warning: This overlay performs configuration from clean sheet.
+ * It is assumed that it is applied after core_init.overlay file.
+ */
+
+&clk_hsi {
+	status = "okay";
+	hsi-div = <1>;
+};
+
+&perck {
+	clocks = <&rcc STM32_SRC_HSI_KER CKPER_SEL(0)>;
+	status = "okay";
+};
+
+&spi1 {
+	/delete-property/ clocks;
+	clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>,
+		 <&rcc STM32_SRC_CKPER SPI123_SEL(4)>;
+	clock-names = "reg", "kernel";
+	status = "okay";
+};

tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/boards/spi1_per_ck_hsi.overlay

@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2021 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Warning: This overlay performs configuration from clean sheet.
+ * It is assumed that it is applied after core_init.overlay file.
+ */
+
+&clk_hsi {
+	status = "okay";
+	hsi-div = <8>;		/* HSI RC: 64MHz, hsi_clk = 8MHz */
+};
+
+&perck {
+	clocks = <&rcc STM32_SRC_HSI_KER CKPER_SEL(0)>;
+	status = "okay";
+};
+
+&spi1 {
+	/delete-property/ clocks;
+	clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>,
+		 <&rcc STM32_SRC_CKPER SPI123_SEL(4)>;
+	clock-names = "reg", "kernel";
+	status = "okay";
+};

tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/src/test_stm32_clock_configuration.c

@@ -75,6 +75,10 @@ static void test_spi_clk_config(void)
 			zassert_equal(spi1_actual_clk_src, RCC_SPI123CLKSOURCE_PLL3,
 					"Expected SPI src: PLLQ (%d). Actual SPI src: %d",
 					spi1_actual_clk_src, RCC_SPI123CLKSOURCE_PLL3);
+		} else if (spi1_dt_ker_clk_src == STM32_SRC_CKPER) {
+			zassert_equal(spi1_actual_clk_src, RCC_SPI123CLKSOURCE_CLKP,
+					"Expected SPI src: PLLQ (%d). Actual SPI src: %d",
+					spi1_actual_clk_src, RCC_SPI123CLKSOURCE_CLKP);
 		} else {
 			zassert_true(1, "Unexpected ker_clk src(%d)", spi1_dt_ker_clk_src);
 		}
@@ -104,6 +108,8 @@ static void test_spi_clk_config(void)
 				spi1_dt_clk_freq, spi1_actual_clk_freq);
 	}
 
+	TC_PRINT("SPI1 clock freq: %d(MHz)\n", spi1_actual_clk_freq / (1000*1000));
+
 	/* Test clock_off(reg_clk) */
 	r = clock_control_off(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
 				(clock_control_subsys_t) &spi1_reg_clk_cfg);

tests/drivers/clock_control/stm32_clock_configuration/stm32h7_devices/testcase.yaml

@@ -8,3 +8,7 @@ tests:
     extra_args: DTC_OVERLAY_FILE="boards/core_init.overlay;boards/spi1_pllq_2_d1ppre_4.overlay"
   drivers.stm32_clock_configuration.h7_dev.spi1_pll3p_1_d1ppre_4:
     extra_args: DTC_OVERLAY_FILE="boards/core_init.overlay;boards/spi1_pll3p_1_d1ppre_4.overlay"
+  drivers.stm32_clock_configuration.h7_dev.spi1_per_ck_d1ppre_1:
+    extra_args: DTC_OVERLAY_FILE="boards/core_init.overlay;boards/spi1_per_ck_d1ppre_1.overlay"
+  drivers.stm32_clock_configuration.h7_dev.spi1_per_ck_hsi:
+    extra_args: DTC_OVERLAY_FILE="boards/core_init.overlay;boards/spi1_per_ck_hsi.overlay"