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boards: arm: mps3: Fix NS flash layout and SRAM size
The mps3/foo/ns configuration defines flash layouts in TF-M to support CONFIG_TFM_MCUBOOT_IMAGE_NUMBER values of 1 or 2. In the Zephyr project, when building samples, the selected value is 2. The layout changes are necessary to support the --max-sectors option when signing images, ensuring that the flash layout is respected. To enable this, the compatible "soc-nv-flash" was added to the reserved memory, and fixed-partitions were defined. Additionally, the ISRAM was redefined to expose the correct size and values for both S and NS firmware, clarifying memory selection for the user. For example, see general details in: https://git.trustedfirmware.org/plugins/gitiles/TF-M/trusted-firmware-m.git/%2B/refs/heads/main/platform/ext/target/arm/mps3/corstone310/common/partition/region_defs.h#116 https://git.trustedfirmware.org/plugins/gitiles/TF-M/trusted-firmware-m.git/%2B/refs/heads/main/platform/ext/target/arm/mps3/corstone310/common/config.cmake#13 Note: - Not all mps3 ISRAM have the same size and design should take that in consideration. Signed-off-by: BUDKE Gerson Fernando <[email protected]>
1 parent a993e1e commit 34320df

12 files changed

+154
-127
lines changed

‎boards/arm/mps3/Kconfig.defconfig‎

Lines changed: 19 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,16 @@
22
# Copyright 2024-2025 Arm Limited and/or its affiliates <[email protected]>
33
# SPDX-License-Identifier: Apache-2.0
44

5-
if BOARD_MPS3_CORSTONE300_AN547 || BOARD_MPS3_CORSTONE300_AN552 || BOARD_MPS3_CORSTONE300_FVP || BOARD_MPS3_CORSTONE310_AN555 || BOARD_MPS3_CORSTONE310_FVP
5+
if BOARD_MPS3_CORSTONE300_AN547 || \
6+
BOARD_MPS3_CORSTONE300_AN547_NS || \
7+
BOARD_MPS3_CORSTONE300_AN552 || \
8+
BOARD_MPS3_CORSTONE300_AN552_NS || \
9+
BOARD_MPS3_CORSTONE300_FVP || \
10+
BOARD_MPS3_CORSTONE300_FVP_NS || \
11+
BOARD_MPS3_CORSTONE310_AN555 || \
12+
BOARD_MPS3_CORSTONE310_AN555_NS || \
13+
BOARD_MPS3_CORSTONE310_FVP || \
14+
BOARD_MPS3_CORSTONE310_FVP_NS
615

716
# MPU-based null-pointer dereferencing detection cannot
817
# be applied as the (0x0 - 0x400) is unmapped but QEMU
@@ -12,6 +21,15 @@ choice NULL_POINTER_EXCEPTION_DETECTION
1221
default NULL_POINTER_EXCEPTION_DETECTION_NONE if QEMU_TARGET
1322
endchoice
1423

24+
# Get flash configuration for NS image from DT flash partition
25+
config USE_DT_CODE_PARTITION
26+
default y if TRUSTED_EXECUTION_NONSECURE
27+
28+
# By default, if we build for a Non-Secure version of the board,
29+
# force building with TF-M as the Secure Execution Environment.
30+
config BUILD_WITH_TFM
31+
default y if TRUSTED_EXECUTION_NONSECURE
32+
1533
if SERIAL
1634

1735
config UART_INTERRUPT_DRIVEN

‎boards/arm/mps3/mps3_common_ns.dtsi‎

Lines changed: 49 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,49 @@
1+
/*
2+
* Copyright 2025 Leica Geosystem AG
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
/ {
8+
reserved_memory: reserved-memory@28000000 {
9+
compatible = "soc-nv-flash";
10+
reg = <0x28000000 DT_SIZE_M(8)>;
11+
erase-block-size = <65536>;
12+
write-block-size = <4>;
13+
#address-cells = <1>;
14+
#size-cells = <1>;
15+
16+
partitions {
17+
compatible = "fixed-partitions";
18+
#address-cells = <1>;
19+
#size-cells = <1>;
20+
21+
/* This code memory region must match what the TF-M
22+
* project has defined for that board - the multi image
23+
* boot is used in Zephyr. See memory layout details in:
24+
*
25+
* https://git.trustedfirmware.org/plugins/gitiles/TF-M/trusted-firmware-m.git/+/refs/heads/main/platform/ext/target/arm/mps3/corstone300/common/partition/flash_layout.h
26+
* https://git.trustedfirmware.org/plugins/gitiles/TF-M/trusted-firmware-m.git/+/refs/heads/main/platform/ext/target/arm/mps3/corstone310/common/partition/flash_layout.h
27+
*/
28+
slot0_partition: partition@0 {
29+
reg = <0x00000000 DT_SIZE_K(512)>;
30+
};
31+
32+
slot0_ns_partition: partition@80000 {
33+
reg = <0x00080000 DT_SIZE_M(3)>;
34+
};
35+
36+
slot1_partition: partition@380000 {
37+
reg = <0x00380000 DT_SIZE_K(512)>;
38+
};
39+
40+
slot1_ns_partition: partition@400000 {
41+
reg = <0x00400000 DT_SIZE_M(3)>;
42+
};
43+
44+
scratch_partition: partition@700000 {
45+
reg = <0x00700000 DT_SIZE_K(512)>;
46+
};
47+
};
48+
};
49+
};

‎boards/arm/mps3/mps3_corstone300_an547_ns.dts‎

Lines changed: 15 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,8 @@
1212
#include <zephyr/dt-bindings/input/input-event-codes.h>
1313
#include <mem.h>
1414

15+
#include "mps3_common_ns.dtsi"
16+
1517
/ {
1618
compatible = "arm,mps3-an547";
1719
#address-cells = <1>;
@@ -20,8 +22,9 @@
2022
chosen {
2123
zephyr,console = &uart0;
2224
zephyr,shell-uart = &uart0;
23-
zephyr,sram = &ram;
24-
zephyr,flash = &code;
25+
zephyr,sram = &isram_ns;
26+
zephyr,flash = &reserved_memory;
27+
zephyr,code-partition = &slot0_ns_partition;
2528
};
2629

2730
cpus {
@@ -63,30 +66,19 @@
6366
zephyr,memory-region = "DTCM";
6467
};
6568

66-
isram: sram@21000000 {
69+
/* The ISRAM blocks are used for both S and NS data. The S reserves 128k
70+
* bytes and the remaining can be used by the NS firmware.
71+
*/
72+
isram_s: secure_data@21000000 {
6773
compatible = "zephyr,memory-region", "mmio-sram";
68-
reg = <0x21000000 DT_SIZE_M(4)>;
69-
zephyr,memory-region = "ISRAM";
74+
reg = <0x21000000 DT_SIZE_K(128)>;
75+
zephyr,memory-region = "ISRAM-Secure";
7076
};
7177

72-
reserved-memory {
73-
#address-cells = <1>;
74-
#size-cells = <1>;
75-
ranges;
76-
77-
/* The memory regions defined below must match what the TF-M
78-
* project has defined for that board - a single image boot is
79-
* assumed. Please see the memory layout in:
80-
* https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/ext/target/mps3/corstone300/common/partition/flash_layout.h
81-
*/
82-
83-
code: memory@28080000 {
84-
reg = <0x28080000 DT_SIZE_K(512)>;
85-
};
86-
87-
ram: memory@21020000 {
88-
reg = <0x21020000 DT_SIZE_M(2)>;
89-
};
78+
isram_ns: non_secure_data@21020000 {
79+
compatible = "zephyr,memory-region", "mmio-sram";
80+
reg = <0x21020000 (DT_SIZE_M(4) - DT_SIZE_K(128))>;
81+
zephyr,memory-region = "ISRAM-Non-Secure";
9082
};
9183

9284
soc {

‎boards/arm/mps3/mps3_corstone300_an547_ns.yaml‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -9,8 +9,8 @@ identifier: mps3/corstone300/an547/ns
99
name: Arm MPS3-Corstone300-AN547_ns
1010
type: mcu
1111
arch: arm
12-
ram: 2048
13-
flash: 512
12+
ram: 3968
13+
flash: 3072
1414
toolchain:
1515
- gnuarmemb
1616
- zephyr

‎boards/arm/mps3/mps3_corstone300_an552_ns.dts‎

Lines changed: 15 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,8 @@
1111
#include <zephyr/dt-bindings/input/input-event-codes.h>
1212
#include <mem.h>
1313

14+
#include "mps3_common_ns.dtsi"
15+
1416
/ {
1517
compatible = "arm,mps3-an552";
1618
#address-cells = <1>;
@@ -19,8 +21,9 @@
1921
chosen {
2022
zephyr,console = &uart0;
2123
zephyr,shell-uart = &uart0;
22-
zephyr,sram = &ram;
23-
zephyr,flash = &code;
24+
zephyr,sram = &isram_ns;
25+
zephyr,flash = &reserved_memory;
26+
zephyr,code-partition = &slot0_ns_partition;
2427
};
2528

2629
cpus {
@@ -62,30 +65,19 @@
6265
zephyr,memory-region = "DTCM";
6366
};
6467

65-
isram: sram@21000000 {
68+
/* The ISRAM blocks are used for both S and NS data. The S reserves 128k
69+
* bytes and the remaining can be used by the NS firmware.
70+
*/
71+
isram_s: secure_data@21000000 {
6672
compatible = "zephyr,memory-region", "mmio-sram";
67-
reg = <0x21000000 DT_SIZE_M(2)>;
68-
zephyr,memory-region = "ISRAM";
73+
reg = <0x21000000 DT_SIZE_K(128)>;
74+
zephyr,memory-region = "ISRAM-Secure";
6975
};
7076

71-
reserved-memory {
72-
#address-cells = <1>;
73-
#size-cells = <1>;
74-
ranges;
75-
76-
/* The memory regions defined below must match what the TF-M
77-
* project has defined for that board - a single image boot is
78-
* assumed. Please see the memory layout in:
79-
* https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/ext/target/mps3/corstone300/common/partition/flash_layout.h
80-
*/
81-
82-
code: memory@28080000 {
83-
reg = <0x28080000 DT_SIZE_K(512)>;
84-
};
85-
86-
ram: memory@21020000 {
87-
reg = <0x21020000 DT_SIZE_M(1)>;
88-
};
77+
isram_ns: non_secure_data@21020000 {
78+
compatible = "zephyr,memory-region", "mmio-sram";
79+
reg = <0x21020000 (DT_SIZE_M(2) - DT_SIZE_K(128))>;
80+
zephyr,memory-region = "ISRAM-Non-Secure";
8981
};
9082

9183
soc {

‎boards/arm/mps3/mps3_corstone300_an552_ns.yaml‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,8 @@ identifier: mps3/corstone300/an552/ns
55
name: Arm MPS3-Corstone300-AN552_ns
66
type: mcu
77
arch: arm
8-
ram: 2048
9-
flash: 512
8+
ram: 1920
9+
flash: 3072
1010
toolchain:
1111
- gnuarmemb
1212
- zephyr

‎boards/arm/mps3/mps3_corstone300_fvp_ns.dts‎

Lines changed: 15 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,8 @@
1111
#include <zephyr/dt-bindings/input/input-event-codes.h>
1212
#include <mem.h>
1313

14+
#include "mps3_common_ns.dtsi"
15+
1416
/ {
1517
compatible = "arm,mps3-fvp";
1618
#address-cells = <1>;
@@ -19,8 +21,9 @@
1921
chosen {
2022
zephyr,console = &uart0;
2123
zephyr,shell-uart = &uart0;
22-
zephyr,sram = &ram;
23-
zephyr,flash = &code;
24+
zephyr,sram = &isram_ns;
25+
zephyr,flash = &reserved_memory;
26+
zephyr,code-partition = &slot0_ns_partition;
2427
};
2528

2629
cpus {
@@ -62,30 +65,19 @@
6265
zephyr,memory-region = "DTCM";
6366
};
6467

65-
isram: sram@21000000 {
68+
/* The ISRAM blocks are used for both S and NS data. The S reserves 128k
69+
* bytes and the remaining can be used by the NS firmware.
70+
*/
71+
isram_s: secure_data@21000000 {
6672
compatible = "zephyr,memory-region", "mmio-sram";
67-
reg = <0x21000000 DT_SIZE_M(2)>;
68-
zephyr,memory-region = "ISRAM";
73+
reg = <0x21000000 DT_SIZE_K(128)>;
74+
zephyr,memory-region = "ISRAM-Secure";
6975
};
7076

71-
reserved-memory {
72-
#address-cells = <1>;
73-
#size-cells = <1>;
74-
ranges;
75-
76-
/* The memory regions defined below must match what the TF-M
77-
* project has defined for that board - a single image boot is
78-
* assumed. Please see the memory layout in:
79-
* https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/ext/target/mps3/corstone300/common/partition/flash_layout.h
80-
*/
81-
82-
code: memory@28080000 {
83-
reg = <0x28080000 DT_SIZE_K(512)>;
84-
};
85-
86-
ram: memory@21020000 {
87-
reg = <0x21020000 DT_SIZE_M(1)>;
88-
};
77+
isram_ns: non_secure_data@21020000 {
78+
compatible = "zephyr,memory-region", "mmio-sram";
79+
reg = <0x21020000 (DT_SIZE_M(2) - DT_SIZE_K(128))>;
80+
zephyr,memory-region = "ISRAM-Non-Secure";
8981
};
9082

9183
soc {

‎boards/arm/mps3/mps3_corstone300_fvp_ns.yaml‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,8 @@ identifier: mps3/corstone300/fvp/ns
55
name: Arm MPS3-Corstone300-FVP_ns
66
type: mcu
77
arch: arm
8-
ram: 2048
9-
flash: 512
8+
ram: 1920
9+
flash: 3072
1010
toolchain:
1111
- gnuarmemb
1212
- zephyr

‎boards/arm/mps3/mps3_corstone310_an555_ns.dts‎

Lines changed: 16 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,8 @@
1111
#include <zephyr/dt-bindings/input/input-event-codes.h>
1212
#include <mem.h>
1313

14+
#include "mps3_common_ns.dtsi"
15+
1416
/ {
1517
compatible = "arm,mps3-an555";
1618
#address-cells = <1>;
@@ -19,8 +21,9 @@
1921
chosen {
2022
zephyr,console = &uart0;
2123
zephyr,shell-uart = &uart0;
22-
zephyr,sram = &ram;
23-
zephyr,flash = &code;
24+
zephyr,sram = &isram_ns;
25+
zephyr,flash = &reserved_memory;
26+
zephyr,code-partition = &slot0_ns_partition;
2427
};
2528

2629
cpus {
@@ -58,34 +61,23 @@
5861

5962
dtcm: dtcm@20000000 {
6063
compatible = "zephyr,memory-region";
61-
reg = <0x20000000 DT_SIZE_K(512)>;
64+
reg = <0x20000000 DT_SIZE_K(32)>;
6265
zephyr,memory-region = "DTCM";
6366
};
6467

65-
isram: sram@21000000 {
68+
/* The ISRAM blocks are used for both S and NS data. The S reserves 128k
69+
* bytes and the remaining can be used by the NS firmware.
70+
*/
71+
isram_s: secure_data@21000000 {
6672
compatible = "zephyr,memory-region", "mmio-sram";
67-
reg = <0x21000000 DT_SIZE_M(4)>;
68-
zephyr,memory-region = "ISRAM";
73+
reg = <0x21000000 DT_SIZE_K(128)>;
74+
zephyr,memory-region = "ISRAM-Secure";
6975
};
7076

71-
reserved-memory {
72-
#address-cells = <1>;
73-
#size-cells = <1>;
74-
ranges;
75-
76-
/* The memory regions defined below must match what the TF-M
77-
* project has defined for that board - a single image boot is
78-
* assumed. Please see the memory layout in:
79-
* https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/platform/ext/target/mps3/corstone310/common/partition/flash_layout.h
80-
*/
81-
82-
code: memory@1000000 {
83-
reg = <0x01000000 DT_SIZE_M(2)>;
84-
};
85-
86-
ram: memory@21000000 {
87-
reg = <0x21000000 DT_SIZE_M(4)>;
88-
};
77+
isram_ns: non_secure_data@21020000 {
78+
compatible = "zephyr,memory-region", "mmio-sram";
79+
reg = <0x21020000 (DT_SIZE_M(4) - DT_SIZE_K(128))>;
80+
zephyr,memory-region = "ISRAM-Non-Secure";
8981
};
9082

9183
soc {

‎boards/arm/mps3/mps3_corstone310_an555_ns.yaml‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,8 @@ identifier: mps3/corstone310/an555/ns
55
name: Arm MPS3-Corstone310-AN555_ns
66
type: mcu
77
arch: arm
8-
ram: 32
9-
flash: 32
8+
ram: 3968
9+
flash: 3072
1010
toolchain:
1111
- gnuarmemb
1212
- zephyr

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