|
8 | 8 | #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
|
9 | 9 | #include <zephyr/linker/linker-defs.h>
|
10 | 10 | #include <string.h>
|
| 11 | +#include <DA1469xAB.h> |
| 12 | +#include <da1469x_clock.h> |
| 13 | +#include <da1469x_otp.h> |
| 14 | +#include <da1469x_pd.h> |
| 15 | +#include <da1469x_pdc.h> |
| 16 | +#include <da1469x_trimv.h> |
11 | 17 |
|
12 | 18 | #define REMAP_ADR0_QSPI 0x2
|
13 | 19 |
|
@@ -107,17 +113,47 @@ void z_arm_platform_init(void)
|
107 | 113 | #endif
|
108 | 114 | }
|
109 | 115 |
|
110 |
| -static int renesas_da14699_init(void) |
| 116 | +static int renesas_da1469x_init(void) |
111 | 117 | {
|
112 | 118 | /* Freeze watchdog until configured */
|
113 | 119 | GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_SYS_WDOG_Msk;
|
| 120 | + |
114 | 121 | /* Reset clock dividers to 0 */
|
115 | 122 | CRG_TOP->CLK_AMBA_REG &= ~(CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Msk |
|
116 |
| - CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Msk); |
117 |
| - /* Enable all power domains except for radio */ |
118 |
| - CRG_TOP->PMU_CTRL_REG = 0x02; |
| 123 | + CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Msk); |
| 124 | + |
| 125 | + CRG_TOP->PMU_CTRL_REG |= (CRG_TOP_PMU_CTRL_REG_TIM_SLEEP_Msk | |
| 126 | + CRG_TOP_PMU_CTRL_REG_PERIPH_SLEEP_Msk | |
| 127 | + CRG_TOP_PMU_CTRL_REG_COM_SLEEP_Msk | |
| 128 | + CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Msk); |
| 129 | + |
| 130 | + /* PDC should take care of PD_SYS */ |
| 131 | + CRG_TOP->PMU_CTRL_REG &= ~CRG_TOP_PMU_CTRL_REG_SYS_SLEEP_Msk; |
| 132 | + |
| 133 | + /* |
| 134 | + * Due to crosstalk issues any power rail can potentially |
| 135 | + * issue a fake event. This is typically observed upon |
| 136 | + * switching power sources, that is DCDC <--> LDOs <--> Retention LDOs. |
| 137 | + */ |
| 138 | + CRG_TOP->BOD_CTRL_REG &= ~(CRG_TOP_BOD_CTRL_REG_BOD_V14_EN_Msk | |
| 139 | + CRG_TOP_BOD_CTRL_REG_BOD_V18F_EN_Msk | |
| 140 | + CRG_TOP_BOD_CTRL_REG_BOD_VDD_EN_Msk | |
| 141 | + CRG_TOP_BOD_CTRL_REG_BOD_V18P_EN_Msk | |
| 142 | + CRG_TOP_BOD_CTRL_REG_BOD_V18_EN_Msk | |
| 143 | + CRG_TOP_BOD_CTRL_REG_BOD_V30_EN_Msk | |
| 144 | + CRG_TOP_BOD_CTRL_REG_BOD_VBAT_EN_Msk); |
| 145 | + |
| 146 | + da1469x_pdc_reset(); |
| 147 | + |
| 148 | + da1469x_otp_init(); |
| 149 | + da1469x_trimv_init_from_otp(); |
| 150 | + |
| 151 | + da1469x_pd_init(); |
| 152 | + da1469x_pd_acquire(MCU_PD_DOMAIN_SYS); |
| 153 | + da1469x_pd_acquire(MCU_PD_DOMAIN_TIM); |
| 154 | + da1469x_pd_acquire(MCU_PD_DOMAIN_COM); |
119 | 155 |
|
120 | 156 | return 0;
|
121 | 157 | }
|
122 | 158 |
|
123 |
| -SYS_INIT(renesas_da14699_init, PRE_KERNEL_1, 0); |
| 159 | +SYS_INIT(renesas_da1469x_init, PRE_KERNEL_1, 0); |
0 commit comments