drivers: flash: stm32_ospi: cleanup STM32H5-related quirks

STM32H5 series now uses the dedicated `flash_stm32_xspi` driver instead.
Remove all quirks related to H5 in the STM32 OSPI driver.

Signed-off-by: Mathieu Choplain <[email protected]>

Author: mathieuchopstm

drivers/flash/Kconfig.stm32_ospi

@@ -9,9 +9,8 @@ config FLASH_STM32_OSPI
 	bool "STM32 Octo SPI Flash driver"
 	default y
 	depends on DT_HAS_ST_STM32_OSPI_NOR_ENABLED
-	select USE_STM32_HAL_OSPI if !SOC_SERIES_STM32H5X
-	select USE_STM32_HAL_XSPI if SOC_SERIES_STM32H5X
-	select USE_STM32_LL_DLYB if (SOC_SERIES_STM32H5X || SOC_SERIES_STM32U5X)
+	select USE_STM32_HAL_OSPI
+	select USE_STM32_LL_DLYB if SOC_SERIES_STM32U5X
 	select USE_STM32_HAL_MDMA if SOC_SERIES_STM32H7X
 	select FLASH_HAS_DRIVER_ENABLED
 	select FLASH_JESD216

drivers/flash/flash_stm32_ospi.c

@@ -25,8 +25,6 @@
 #include "spi_nor.h"
 #include "jesd216.h"
 
-#include "flash_stm32_ospi.h"
-
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(flash_stm32_ospi, CONFIG_FLASH_LOG_LEVEL);
 
@@ -57,17 +55,10 @@ LOG_MODULE_REGISTER(flash_stm32_ospi, CONFIG_FLASH_LOG_LEVEL);
 
 #define STM32_OSPI_FIFO_THRESHOLD         4
 
-#if defined(CONFIG_SOC_SERIES_STM32H5X)
-/* Valid range is [0, 255] */
-#define STM32_OSPI_CLOCK_PRESCALER_MIN  0U
-#define STM32_OSPI_CLOCK_PRESCALER_MAX  255U
-#define STM32_OSPI_CLOCK_COMPUTE(bus_freq, prescaler) ((bus_freq) / ((prescaler) + 1U))
-#else
 /* Valid range is [1, 256] */
 #define STM32_OSPI_CLOCK_PRESCALER_MIN  1U
 #define STM32_OSPI_CLOCK_PRESCALER_MAX  256U
 #define STM32_OSPI_CLOCK_COMPUTE(bus_freq, prescaler) ((bus_freq) / (prescaler))
-#endif
 
 /* Max Time value during reset or erase operation */
 #define STM32_OSPI_RESET_MAX_TIME               100U
@@ -2355,13 +2346,8 @@ static int flash_stm32_ospi_init(const struct device *dev)
 	/* Initialize OSPI HAL structure completely */
 	dev_data->hospi.Init.FifoThreshold = 4;
 	dev_data->hospi.Init.ClockPrescaler = prescaler;
-#if defined(CONFIG_SOC_SERIES_STM32H5X)
-	/* The stm32h5xx_hal_xspi does not reduce DEVSIZE before writing the DCR1 */
-	dev_data->hospi.Init.DeviceSize = find_lsb_set(dev_cfg->flash_size) - 2;
-#else
 	/* Give a bit position from 0 to 31 to the HAL init for the DCR1 reg */
 	dev_data->hospi.Init.DeviceSize = find_lsb_set(dev_cfg->flash_size) - 1;
-#endif /* CONFIG_SOC_SERIES_STM32U5X */
 	dev_data->hospi.Init.DualQuad = HAL_OSPI_DUALQUAD_DISABLE;
 	dev_data->hospi.Init.ChipSelectHighTime = 2;
 	dev_data->hospi.Init.FreeRunningClock = HAL_OSPI_FREERUNCLK_DISABLE;
@@ -2437,23 +2423,6 @@ static int flash_stm32_ospi_init(const struct device *dev)
 
 #endif /* OCTOSPIM */
 
-#if defined(CONFIG_SOC_SERIES_STM32H5X)
-	/* OCTOSPI1 delay block init Function */
-	HAL_XSPI_DLYB_CfgTypeDef xspi_delay_block_cfg = {0};
-
-	(void)HAL_XSPI_DLYB_GetClockPeriod(&dev_data->hospi, &xspi_delay_block_cfg);
-	/*  with DTR, set the PhaseSel/4 (empiric value from stm32Cube) */
-	xspi_delay_block_cfg.PhaseSel /= 4;
-
-	if (HAL_XSPI_DLYB_SetConfig(&dev_data->hospi, &xspi_delay_block_cfg) != HAL_OK) {
-		LOG_ERR("XSPI DelayBlock failed");
-		return -EIO;
-	}
-
-	LOG_DBG("Delay Block Init");
-
-#endif /* CONFIG_SOC_SERIES_STM32H5X */
-
 	/* Initialize semaphores */
 	k_sem_init(&dev_data->sem, 1, 1);
 	k_sem_init(&dev_data->sync, 0, 1);