@@ -201,8 +201,6 @@ struct uhc_dwc2_data {
201201 /* Main events the driver thread waits for */
202202 struct k_event drv_evt ;
203203 struct uhc_dwc2_chan chan [UHC_DWC2_MAX_CHAN ];
204- /* Number of channels currently allocated */
205- size_t num_channels ;
206204 /* Bit mask of channels with pending interrupts */
207205 uint32_t pending_channel_intrs_msk ;
208206 /* Data, that is used in multiple threads */
@@ -835,7 +833,6 @@ static int uhc_dwc2_init_controller(const struct device *dev)
835833 priv -> last_event = UHC_PORT_EVENT_NONE ;
836834
837835 /* TODO: Clear all the flags and channels */
838- priv -> num_channels = 0 ;
839836 priv -> pending_channel_intrs_msk = 0 ;
840837
841838 return 0 ;
@@ -1635,55 +1632,19 @@ static inline void uhc_dwc2_submit_dev_gone(const struct device *dev)
16351632 uhc_submit_event (dev , UHC_EVT_DEV_REMOVED , 0 );
16361633}
16371634
1638- /*
1639- * Adds the channel object to the channel list and initializes it.
1640- */
1641- static inline bool uhc_dwc2_chan_init (const struct device * dev , struct uhc_dwc2_chan * chan )
1642- {
1643- const struct uhc_dwc2_config * const config = dev -> config ;
1644- struct uhc_dwc2_data * priv = uhc_get_private (dev );
1645- struct usb_dwc2_reg * const dwc2 = config -> base ;
1646- const struct usb_dwc2_host_chan * chan_regs ;
1647-
1648- /* TODO: FIFO sizes should be set before attempting to allocate a channel */
1649-
1650- if (priv -> num_channels == UHC_DWC2_NUMHSTCHNL (config )) {
1651- return false;
1652- }
1653-
1654- chan -> chan_idx = priv -> num_channels ;
1655- priv -> num_channels ++ ;
1656-
1657- chan_regs = UHC_DWC2_CHAN_REG (dwc2 , chan -> chan_idx );
1658-
1659- LOG_DBG ("Allocating channel %d" , chan -> chan_idx );
1660-
1661- /* Init underlying channel registers */
1662-
1663- /* Clear the interrupt bits by writing them back */
1664- uint32_t hcint = sys_read32 ((mem_addr_t )& chan_regs -> hcint );
1665- sys_write32 (hcint , (mem_addr_t )& chan_regs -> hcint );
1666-
1667- /* Enable channel interrupts in the core */
1668- sys_set_bits ((mem_addr_t )& dwc2 -> haintmsk , (1 << chan -> chan_idx ));
1669-
1670- /* Enable transfer complete and channel halted interrupts */
1671- sys_set_bits ((mem_addr_t )& chan_regs -> hcintmsk ,
1672- USB_DWC2_HCINT_XFERCOMPL | USB_DWC2_HCINT_CHHLTD );
1673- return true;
1674- }
1675-
16761635/*
16771636 * Allocate a chan holding the underlying channel object and the DMA buffer for transfer purposes.
16781637 */
1679- static inline int uhc_dwc2_chan_alloc (const struct device * dev , uint8_t chan_idx , uint8_t ep_addr ,
1680- uint8_t dev_addr , enum uhc_dwc2_speed dev_speed ,
1681- enum uhc_dwc2_speed port_speed , enum uhc_dwc2_xfer_type type )
1638+ static inline int uhc_dwc2_chan_config (const struct device * dev , uint8_t chan_idx , uint8_t ep_addr ,
1639+ uint8_t dev_addr , enum uhc_dwc2_speed dev_speed ,
1640+ enum uhc_dwc2_speed port_speed , enum uhc_dwc2_xfer_type type )
16821641{
16831642 struct uhc_dwc2_data * priv = uhc_get_private (dev );
16841643 /* TODO: Allocate the chan and it's resources */
16851644 struct uhc_dwc2_chan * chan = & priv -> chan [0 ];
1686- /* TODO: Refactor to get port speed, static for now */
1645+ const struct uhc_dwc2_config * const config = dev -> config ;
1646+ struct usb_dwc2_reg * const dwc2 = config -> base ;
1647+ const struct usb_dwc2_host_chan * chan_regs ;
16871648
16881649 /* TODO: Double buffering scheme? */
16891650
@@ -1706,7 +1667,26 @@ static inline int uhc_dwc2_chan_alloc(const struct device *dev, uint8_t chan_idx
17061667 return - ENODEV ;
17071668 }
17081669
1709- uhc_dwc2_chan_init (dev , chan );
1670+ /* TODO: FIFO sizes should be set before attempting to allocate a channel */
1671+
1672+ chan -> chan_idx = chan_idx ;
1673+
1674+ chan_regs = UHC_DWC2_CHAN_REG (dwc2 , chan -> chan_idx );
1675+
1676+ LOG_DBG ("Allocating channel %d" , chan -> chan_idx );
1677+
1678+ /* Init underlying channel registers */
1679+
1680+ /* Clear the interrupt bits by writing them back */
1681+ uint32_t hcint = sys_read32 ((mem_addr_t )& chan_regs -> hcint );
1682+ sys_write32 (hcint , (mem_addr_t )& chan_regs -> hcint );
1683+
1684+ /* Enable channel interrupts in the core */
1685+ sys_set_bits ((mem_addr_t )& dwc2 -> haintmsk , (1 << chan -> chan_idx ));
1686+
1687+ /* Enable transfer complete and channel halted interrupts */
1688+ sys_set_bits ((mem_addr_t )& chan_regs -> hcintmsk ,
1689+ USB_DWC2_HCINT_XFERCOMPL | USB_DWC2_HCINT_CHHLTD );
17101690
17111691 dwc2_channel_configure (dev , chan );
17121692
@@ -1743,12 +1723,7 @@ static inline int uhc_dwc2_chan_deinit(const struct device *dev, struct uhc_dwc2
17431723
17441724 sys_clear_bits ((mem_addr_t )& dwc2 -> haintmsk , (1 << chan -> chan_idx ));
17451725
1746- priv -> num_channels -- ;
1747-
1748- LOG_DBG ("Freeing channel %d, num_channels=%d" , chan -> chan_idx , priv -> num_channels );
1749-
1750- __ASSERT (priv -> num_channels >= 0 , "Number of allocated channels is negative: %d" ,
1751- priv -> num_channels );
1726+ LOG_DBG ("Freeing channel %d" , chan -> chan_idx );
17521727
17531728 /* TODO: Remove the chan from the list of idle chans in the port object */
17541729 priv -> num_chans_idle -- ;
@@ -1778,22 +1753,23 @@ static inline void uhc_dwc2_handle_port_events(const struct device *dev)
17781753 priv -> port_state = UHC_PORT_STATE_ENABLED ;
17791754 /* TODO: exit critical section */
17801755
1781- enum uhc_dwc2_speed speed ;
1756+ enum uhc_dwc2_speed port_speed ;
17821757
1783- ret = uhc_dwc2_get_port_speed (dev , & speed );
1758+ ret = uhc_dwc2_get_port_speed (dev , & port_speed );
17841759 if (ret ) {
17851760 LOG_ERR ("Failed to get port speed" );
17861761 break ;
17871762 }
17881763
1789- ret = uhc_dwc2_chan_alloc (dev , 0 , 0 , 0 , UHC_DWC2_SPEED_FULL , UHC_DWC2_SPEED_FULL ,
1790- UHC_DWC2_XFER_TYPE_CTRL );
1764+ ret = uhc_dwc2_chan_config (dev , 0 , 0 , 0 , UHC_DWC2_SPEED_FULL , port_speed ,
1765+ UHC_DWC2_XFER_TYPE_CTRL );
17911766 if (ret ) {
17921767 LOG_ERR ("Failed to initialize channels: %d" , ret );
17931768 break ;
17941769 }
1770+
17951771 /* Notify the higher logic about the new device */
1796- uhc_dwc2_submit_new_device (dev , speed );
1772+ uhc_dwc2_submit_new_device (dev , port_speed );
17971773 break ;
17981774 }
17991775 case UHC_PORT_EVENT_DISCONNECTION :
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