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LaurentiuM1234kartben
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dts: xtensa: nxp_imx8: add edma power domains
Add power domains for EDMA0's channels 6, 7, 14, and 15. For QM these are identified as IMX_SC_R_DMA_2_*, while for QXP thy are identified as IMX_SC_R_DMA_0_*. Signed-off-by: Laurentiu Mihalcea <[email protected]>
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dts/xtensa/nxp/nxp_imx8.dtsi

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@@ -55,6 +55,62 @@
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nxp,resource-id = <IMX_SC_R_IRQSTR_DSP>;
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#power-domain-cells = <0>;
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};
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edma0_ch6_pd: pd@1 {
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compatible = "nxp,imx8qm-scu-pd", "nxp,scu-pd";
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reg = <1>;
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nxp,resource-id = <IMX_SC_R_DMA_0_CH6>;
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#power-domain-cells = <0>;
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};
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edma0_ch7_pd: pd@2 {
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compatible = "nxp,imx8qm-scu-pd", "nxp,scu-pd";
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reg = <2>;
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nxp,resource-id = <IMX_SC_R_DMA_0_CH7>;
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#power-domain-cells = <0>;
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};
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edma0_ch14_pd: pd@3 {
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compatible = "nxp,imx8qm-scu-pd", "nxp,scu-pd";
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reg = <3>;
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nxp,resource-id = <IMX_SC_R_DMA_0_CH14>;
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#power-domain-cells = <0>;
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};
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edma0_ch15_pd: pd@4 {
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compatible = "nxp,imx8qm-scu-pd", "nxp,scu-pd";
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reg = <4>;
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nxp,resource-id = <IMX_SC_R_DMA_0_CH15>;
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#power-domain-cells = <0>;
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};
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edma2_ch6_pd: pd@5 {
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compatible = "nxp,imx8qm-scu-pd", "nxp,scu-pd";
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reg = <5>;
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nxp,resource-id = <IMX_SC_R_DMA_2_CH6>;
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#power-domain-cells = <0>;
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};
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edma2_ch7_pd: pd@6 {
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compatible = "nxp,imx8qm-scu-pd", "nxp,scu-pd";
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reg = <6>;
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nxp,resource-id = <IMX_SC_R_DMA_2_CH7>;
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#power-domain-cells = <0>;
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};
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edma2_ch14_pd: pd@7 {
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compatible = "nxp,imx8qm-scu-pd", "nxp,scu-pd";
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reg = <7>;
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nxp,resource-id = <IMX_SC_R_DMA_2_CH14>;
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#power-domain-cells = <0>;
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};
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edma2_ch15_pd: pd@8 {
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compatible = "nxp,imx8qm-scu-pd", "nxp,scu-pd";
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reg = <8>;
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nxp,resource-id = <IMX_SC_R_DMA_2_CH15>;
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#power-domain-cells = <0>;
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};
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};
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};
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@@ -74,6 +130,8 @@
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compatible = "nxp,edma";
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reg = <0x591f0000 (DT_SIZE_K(64) * 33)>;
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valid-channels = <6>, <7>, <14>, <15>;
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power-domains = <&edma0_ch6_pd>, <&edma0_ch7_pd>,
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<&edma0_ch14_pd>, <&edma0_ch15_pd>;
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interrupts-extended = <&master6 58>, <&master6 58>,
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<&master5 29>, <&master5 29>;
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#dma-cells = <2>;

dts/xtensa/nxp/nxp_imx8qm.dtsi

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@@ -81,3 +81,8 @@
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};
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};
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};
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&edma0 {
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power-domains = <&edma2_ch6_pd>, <&edma2_ch7_pd>,
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<&edma2_ch14_pd>, <&edma2_ch15_pd>;
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};

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