drivers/flash: stm32l5: Adding flash driver for stm32l5x series

This commit adds flash driver in non-secure mode for stm32l5x
series with icache enabled. This commit also adds a flash
programming error status check applicable for all platforms
except stm32f1 series.

Signed-off-by: Krishna Mohan Dani <[email protected]>

Author: ikmdani

drivers/flash/CMakeLists.txt

@@ -43,6 +43,7 @@ if(CONFIG_SOC_FLASH_STM32)
     zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F4X flash_stm32f4x.c)
     zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32F7X flash_stm32f7x.c)
     zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L4X flash_stm32l4x.c)
+    zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32L5X flash_stm32l5x.c)
     zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32WLX flash_stm32l4x.c)
     zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32WBX flash_stm32wbx.c)
     zephyr_sources_ifdef(CONFIG_SOC_SERIES_STM32G0X flash_stm32g0x.c)

drivers/flash/Kconfig.stm32

@@ -7,7 +7,7 @@
 config SOC_FLASH_STM32
 	bool "STM32 flash driver"
 	depends on SOC_FAMILY_STM32
-	depends on (SOC_SERIES_STM32F0X || SOC_SERIES_STM32F1X || SOC_SERIES_STM32F2X || SOC_SERIES_STM32F3X || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32L0X  || SOC_SERIES_STM32L1X || SOC_SERIES_STM32L4X || SOC_SERIES_STM32WBX || SOC_SERIES_STM32WLX || SOC_SERIES_STM32G0X || SOC_SERIES_STM32G4X || SOC_SERIES_STM32H7X)
+	depends on (SOC_SERIES_STM32F0X || SOC_SERIES_STM32F1X || SOC_SERIES_STM32F2X || SOC_SERIES_STM32F3X || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32L0X  || SOC_SERIES_STM32L1X || SOC_SERIES_STM32L4X || SOC_SERIES_STM32L5X || SOC_SERIES_STM32WBX || SOC_SERIES_STM32WLX || SOC_SERIES_STM32G0X || SOC_SERIES_STM32G4X || SOC_SERIES_STM32H7X)
 	select FLASH_HAS_DRIVER_ENABLED
 	default y
 	select SOC_FLASH_STM32_V1 if SOC_SERIES_STM32F0X
@@ -20,6 +20,7 @@ config SOC_FLASH_STM32
 	select FLASH_PAGE_LAYOUT if SOC_SERIES_STM32F4X
 	select FLASH_PAGE_LAYOUT if SOC_SERIES_STM32F7X
 	select FLASH_PAGE_LAYOUT if SOC_SERIES_STM32L4X
+	select FLASH_PAGE_LAYOUT if SOC_SERIES_STM32L5X
 	select FLASH_PAGE_LAYOUT if SOC_SERIES_STM32WBX
 	select FLASH_PAGE_LAYOUT if SOC_SERIES_STM32WLX
 	select FLASH_PAGE_LAYOUT if SOC_SERIES_STM32G4X
@@ -29,15 +30,16 @@ config SOC_FLASH_STM32
 	select FLASH_HAS_PAGE_LAYOUT if SOC_SERIES_STM32F4X
 	select FLASH_HAS_PAGE_LAYOUT if SOC_SERIES_STM32F7X
 	select FLASH_HAS_PAGE_LAYOUT if SOC_SERIES_STM32L4X
+	select FLASH_HAS_PAGE_LAYOUT if SOC_SERIES_STM32L5X
 	select FLASH_HAS_PAGE_LAYOUT if SOC_SERIES_STM32WBX
 	select FLASH_HAS_PAGE_LAYOUT if SOC_SERIES_STM32WLX
 	select FLASH_HAS_PAGE_LAYOUT if SOC_SERIES_STM32G4X
 	select FLASH_HAS_PAGE_LAYOUT if SOC_SERIES_STM32H7X
 	select MPU_ALLOW_FLASH_WRITE if ARM_MPU
 	help
 	  Enable STM32F0x, STM32F1x, STM32F2x, STM32F3x, STM32F4x, STM32F7x,
-	  STM32L0x, STM32L1x, STM32L4x, STM32WBx, STM32WLx, STM32G0x, STM32G4x
-	  or STM3H7x series flash driver.
+	  STM32L0x, STM32L1x, STM32L4x, STM32L5x, STM32WBx, STM32WLx, STM32G0x,
+	  STM32G4x or STM3H7x series flash driver.
 
 config SOC_FLASH_STM32_V1
 	bool

drivers/flash/flash_stm32.c

@@ -29,6 +29,17 @@ LOG_MODULE_REGISTER(flash_stm32, CONFIG_FLASH_LOG_LEVEL);
  */
 #define STM32_FLASH_TIMEOUT	(2 * DT_PROP(DT_INST(0, soc_nv_flash), max_erase_time))
 
+#if defined(FLASH_NSSR_NSBSY)		/* For STM32L5x in non-secure mode */
+#define FLASH_SECURITY_NS
+#elif defined(FLASH_SECSR_SECBSY)	/* For STM32L5x in secured mode */
+#error Flash is not supported in secure mode
+#define FLASH_SECURITY_SEC
+#else
+#define FLASH_SECURITY_NA		/* For series which does not have
+					 *  secured or non-secured mode
+					 */
+#endif
+
 static const struct flash_parameters flash_stm32_parameters = {
 	.write_block_size = FLASH_STM32_WRITE_BLOCK_SIZE,
 	/* Some SoCs (L0/L1) use an EEPROM under the hood. Distinguish
@@ -93,13 +104,21 @@ static int flash_stm32_check_status(const struct device *dev)
 #if defined(FLASH_FLAG_OPERR)
 		FLASH_FLAG_OPERR |
 #endif
+#if defined(FLASH_FLAG_PROGERR)
+		FLASH_FLAG_PROGERR |
+#endif
 #if defined(FLASH_FLAG_PGERR)
 		FLASH_FLAG_PGERR |
 #endif
 		FLASH_FLAG_WRPERR;
 
+#if defined(FLASH_SECURITY_NS)
+	if (FLASH_STM32_REGS(dev)->NSSR & error) {
+		LOG_DBG("Status: 0x%08x", FLASH_STM32_REGS(dev)->NSSR & error);
+#else /* FLASH_SECURITY_SEC | FLASH_SECURITY_NA */
 	if (FLASH_STM32_REGS(dev)->SR & error) {
 		LOG_DBG("Status: 0x%08x", FLASH_STM32_REGS(dev)->SR & error);
+#endif /* FLASH_SECURITY_NS */
 		return -EIO;
 	}
 
@@ -116,11 +135,16 @@ int flash_stm32_wait_flash_idle(const struct device *dev)
 	if (rc < 0) {
 		return -EIO;
 	}
-#if defined(CONFIG_SOC_SERIES_STM32G0X)
+#if defined(FLASH_SECURITY_NS)
+	while ((FLASH_STM32_REGS(dev)->NSSR & FLASH_FLAG_BSY)) {
+#else /* FLASH_SECURITY_SEC | FLASH_SECURITY_NA */
+#if defined(FLASH_SR_BSY1)
+	/* Applicable for STM32G0 series */
 	while ((FLASH_STM32_REGS(dev)->SR & FLASH_SR_BSY1)) {
 #else
 	while ((FLASH_STM32_REGS(dev)->SR & FLASH_SR_BSY)) {
 #endif
+#endif /* FLASH_SECURITY_NS */
 		if (k_uptime_get() > timeout_time) {
 			LOG_ERR("Timeout! val: %d", STM32_FLASH_TIMEOUT);
 			return -EIO;
@@ -134,7 +158,7 @@ static void flash_stm32_flush_caches(const struct device *dev,
 				     off_t offset, size_t len)
 {
 #if defined(CONFIG_SOC_SERIES_STM32F0X) || defined(CONFIG_SOC_SERIES_STM32F3X) || \
-	defined(CONFIG_SOC_SERIES_STM32G0X)
+	defined(CONFIG_SOC_SERIES_STM32G0X) || defined(CONFIG_SOC_SERIES_STM32L5X)
 	ARG_UNUSED(dev);
 	ARG_UNUSED(offset);
 	ARG_UNUSED(len);
@@ -266,6 +290,16 @@ static int flash_stm32_write_protection(const struct device *dev, bool enable)
 		}
 	}
 
+#if defined(FLASH_SECURITY_NS)
+	if (enable) {
+		regs->NSCR |= FLASH_NSCR_NSLOCK;
+	} else {
+		if (regs->NSCR & FLASH_NSCR_NSLOCK) {
+			regs->NSKEYR = FLASH_KEY1;
+			regs->NSKEYR = FLASH_KEY2;
+		}
+	}
+#else	/* FLASH_SECURITY_SEC | FLASH_SECURITY_NA */
 #if defined(FLASH_CR_LOCK)
 	if (enable) {
 		regs->CR |= FLASH_CR_LOCK;
@@ -293,6 +327,7 @@ static int flash_stm32_write_protection(const struct device *dev, bool enable)
 		}
 	}
 #endif
+#endif /* FLASH_SECURITY_NS */
 
 	if (enable) {
 		LOG_DBG("Enable write protection");
@@ -337,7 +372,7 @@ static const struct flash_driver_api flash_stm32_api = {
 static int stm32_flash_init(const struct device *dev)
 {
 	int rc;
-	/* Below is applicable to F0, F1, F3, G0, G4, L1, L4 & WB55 series.
+	/* Below is applicable to F0, F1, F3, G0, G4, L1, L4, L5 & WB55 series.
 	 * For F2, F4, F7 & H7 series, this is not applicable.
 	 */
 #if DT_INST_NODE_HAS_PROP(0, clocks)