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| 1 | +/* |
| 2 | + * Copyright (c) 2021 Yonatan Schachter |
| 3 | + * |
| 4 | + * SPDX-License-Identifier: Apache-2.0 |
| 5 | + */ |
| 6 | + |
| 7 | +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_RP2040_RESET_H_ |
| 8 | +#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_RP2040_RESET_H_ |
| 9 | + |
| 10 | +#define RPI_PICO_RESETS_RESET_ADC 0 |
| 11 | +#define RPI_PICO_RESETS_RESET_BUSCTRL 1 |
| 12 | +#define RPI_PICO_RESETS_RESET_DMA 2 |
| 13 | +#define RPI_PICO_RESETS_RESET_I2C0 3 |
| 14 | +#define RPI_PICO_RESETS_RESET_I2C1 4 |
| 15 | +#define RPI_PICO_RESETS_RESET_IO_BANK0 5 |
| 16 | +#define RPI_PICO_RESETS_RESET_IO_QSPI 6 |
| 17 | +#define RPI_PICO_RESETS_RESET_JTAG 7 |
| 18 | +#define RPI_PICO_RESETS_RESET_PADS_BANK0 8 |
| 19 | +#define RPI_PICO_RESETS_RESET_PADS_QSPI 9 |
| 20 | +#define RPI_PICO_RESETS_RESET_PIO0 10 |
| 21 | +#define RPI_PICO_RESETS_RESET_PIO1 11 |
| 22 | +#define RPI_PICO_RESETS_RESET_PLL_SYS 12 |
| 23 | +#define RPI_PICO_RESETS_RESET_PLL_USB 13 |
| 24 | +#define RPI_PICO_RESETS_RESET_PWM 14 |
| 25 | +#define RPI_PICO_RESETS_RESET_RTC 15 |
| 26 | +#define RPI_PICO_RESETS_RESET_SPI0 16 |
| 27 | +#define RPI_PICO_RESETS_RESET_SPI1 17 |
| 28 | +#define RPI_PICO_RESETS_RESET_SYSCFG 18 |
| 29 | +#define RPI_PICO_RESETS_RESET_SYSINFO 19 |
| 30 | +#define RPI_PICO_RESETS_RESET_TBMAN 20 |
| 31 | +#define RPI_PICO_RESETS_RESET_TIMER 21 |
| 32 | +#define RPI_PICO_RESETS_RESET_UART0 22 |
| 33 | +#define RPI_PICO_RESETS_RESET_UART1 23 |
| 34 | +#define RPI_PICO_RESETS_RESET_USBCTRL 24 |
| 35 | + |
| 36 | +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_RP2040_RESET_H_ */ |
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