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ndrs-pstcarlescufi
ndrs-pst
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carlescufi
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drivers: clock_control: stm32: fix typo
Use a code spell-checking tool to scan and correct spelling errors in the following files: - clock_stm32_ll_common.c - clock_stm32_ll_h5.c - clock_stm32_ll_h7.c - clock_stm32_ll_u5.c - clock_stm32_ll_wba.c Signed-off-by: Pisit Sawangvonganan <[email protected]>
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5 files changed

+21
-21
lines changed

5 files changed

+21
-21
lines changed

‎drivers/clock_control/clock_stm32_ll_common.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -205,7 +205,7 @@ static inline int stm32_clock_control_on(const struct device *dev,
205205
ARG_UNUSED(dev);
206206

207207
if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
208-
/* Attemp to change a wrong periph clock bit */
208+
/* Attempt to change a wrong periph clock bit */
209209
return -ENOTSUP;
210210
}
211211

@@ -228,7 +228,7 @@ static inline int stm32_clock_control_off(const struct device *dev,
228228
ARG_UNUSED(dev);
229229

230230
if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
231-
/* Attemp to toggle a wrong periph clock bit */
231+
/* Attempt to toggle a wrong periph clock bit */
232232
return -ENOTSUP;
233233
}
234234

@@ -750,7 +750,7 @@ int stm32_clock_control_init(const struct device *dev)
750750
}
751751
#endif /* FLASH_ACR_LATENCY */
752752

753-
/* Set up indiviual enabled clocks */
753+
/* Set up individual enabled clocks */
754754
set_up_fixed_clock_sources();
755755

756756
/* Set up PLLs */

‎drivers/clock_control/clock_stm32_ll_h5.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -150,7 +150,7 @@ static inline int stm32_clock_control_on(const struct device *dev,
150150
ARG_UNUSED(dev);
151151

152152
if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
153-
/* Attemp to toggle a wrong periph clock bit */
153+
/* Attempt to toggle a wrong periph clock bit */
154154
return -ENOTSUP;
155155
}
156156

@@ -171,7 +171,7 @@ static inline int stm32_clock_control_off(const struct device *dev,
171171
ARG_UNUSED(dev);
172172

173173
if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
174-
/* Attemp to toggle a wrong periph clock bit */
174+
/* Attempt to toggle a wrong periph clock bit */
175175
return -ENOTSUP;
176176
}
177177

@@ -722,7 +722,7 @@ int stm32_clock_control_init(const struct device *dev)
722722
return r;
723723
}
724724

725-
/* Set peripheral busses prescalers */
725+
/* Set peripheral buses prescalers */
726726
LL_RCC_SetAHBPrescaler(ahb_prescaler(STM32_AHB_PRESCALER));
727727
LL_RCC_SetAPB1Prescaler(apb1_prescaler(STM32_APB1_PRESCALER));
728728
LL_RCC_SetAPB2Prescaler(apb2_prescaler(STM32_APB2_PRESCALER));

‎drivers/clock_control/clock_stm32_ll_h7.c‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -142,7 +142,7 @@
142142
#error "SYS clock frequency for M7 core doesn't match CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC"
143143
#endif
144144

145-
/* end of clock feasability check */
145+
/* end of clock feasibility check */
146146
#endif /* CONFIG_CPU_CORTEX_M7 */
147147

148148

@@ -329,7 +329,7 @@ static uint32_t get_vco_output_range(uint32_t vco_input_range)
329329

330330
#endif /* ! CONFIG_CPU_CORTEX_M4 */
331331

332-
/** @brief Verifies clock is part of actve clock configuration */
332+
/** @brief Verifies clock is part of active clock configuration */
333333
static int enabled_clock(uint32_t src_clk)
334334
{
335335

@@ -365,7 +365,7 @@ static inline int stm32_clock_control_on(const struct device *dev,
365365
ARG_UNUSED(dev);
366366

367367
if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
368-
/* Attemp to toggle a wrong periph clock bit */
368+
/* Attempt to toggle a wrong periph clock bit */
369369
return -ENOTSUP;
370370
}
371371

@@ -391,7 +391,7 @@ static inline int stm32_clock_control_off(const struct device *dev,
391391
ARG_UNUSED(dev);
392392

393393
if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
394-
/* Attemp to toggle a wrong periph clock bit */
394+
/* Attempt to toggle a wrong periph clock bit */
395395
return -ENOTSUP;
396396
}
397397

@@ -416,7 +416,7 @@ static inline int stm32_clock_control_configure(const struct device *dev,
416416

417417
err = enabled_clock(pclken->bus);
418418
if (err < 0) {
419-
/* Attemp to configure a src clock not available or not valid */
419+
/* Attempt to configure a src clock not available or not valid */
420420
return err;
421421
}
422422

@@ -852,7 +852,7 @@ int stm32_clock_control_init(const struct device *dev)
852852
/* Configure MCO1/MCO2 based on Kconfig */
853853
stm32_clock_control_mco_init();
854854

855-
/* Set up indiviual enabled clocks */
855+
/* Set up individual enabled clocks */
856856
set_up_fixed_clock_sources();
857857

858858
/* Set up PLLs */
@@ -877,7 +877,7 @@ int stm32_clock_control_init(const struct device *dev)
877877
LL_SetFlashLatency(new_hclk_freq);
878878
}
879879

880-
/* Preset the prescalers prior to chosing SYSCLK */
880+
/* Preset the prescalers prior to choosing SYSCLK */
881881
/* Prevents APB clock to go over limits */
882882
/* Set buses (Sys,AHB, APB1, APB2 & APB4) prescalers */
883883
LL_RCC_SetSysPrescaler(sysclk_prescaler(STM32_D1CPRE));

‎drivers/clock_control/clock_stm32_ll_u5.c‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -125,7 +125,7 @@ static int enabled_clock(uint32_t src_clk)
125125
if ((src_clk == STM32_SRC_SYSCLK) ||
126126
((src_clk == STM32_SRC_HSE) && IS_ENABLED(STM32_HSE_ENABLED)) ||
127127
((src_clk == STM32_SRC_HSI16) && IS_ENABLED(STM32_HSI_ENABLED)) ||
128-
+ ((src_clk == STM32_SRC_HSI48) && IS_ENABLED(STM32_HSI48_ENABLED)) ||
128+
((src_clk == STM32_SRC_HSI48) && IS_ENABLED(STM32_HSI48_ENABLED)) ||
129129
((src_clk == STM32_SRC_LSE) && IS_ENABLED(STM32_LSE_ENABLED)) ||
130130
((src_clk == STM32_SRC_LSI) && IS_ENABLED(STM32_LSI_ENABLED)) ||
131131
((src_clk == STM32_SRC_MSIS) && IS_ENABLED(STM32_MSIS_ENABLED)) ||
@@ -154,7 +154,7 @@ static inline int stm32_clock_control_on(const struct device *dev,
154154
ARG_UNUSED(dev);
155155

156156
if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
157-
/* Attemp to toggle a wrong periph clock bit */
157+
/* Attempt to toggle a wrong periph clock bit */
158158
return -ENOTSUP;
159159
}
160160

@@ -175,7 +175,7 @@ static inline int stm32_clock_control_off(const struct device *dev,
175175
ARG_UNUSED(dev);
176176

177177
if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
178-
/* Attemp to toggle a wrong periph clock bit */
178+
/* Attempt to toggle a wrong periph clock bit */
179179
return -ENOTSUP;
180180
}
181181

@@ -715,7 +715,7 @@ static void set_up_fixed_clock_sources(void)
715715
while (!LL_RCC_LSE_IsReady()) {
716716
}
717717

718-
/* Enable LSESYS additionnally */
718+
/* Enable LSESYS additionally */
719719
LL_RCC_LSE_EnablePropagation();
720720
/* Wait till LSESYS is ready */
721721
while (!LL_RCC_LSESYS_IsReady()) {
@@ -830,7 +830,7 @@ int stm32_clock_control_init(const struct device *dev)
830830
return r;
831831
}
832832

833-
/* Set peripheral busses prescalers */
833+
/* Set peripheral buses prescalers */
834834
LL_RCC_SetAHBPrescaler(ahb_prescaler(STM32_AHB_PRESCALER));
835835
LL_RCC_SetAPB1Prescaler(apb1_prescaler(STM32_APB1_PRESCALER));
836836
LL_RCC_SetAPB2Prescaler(apb2_prescaler(STM32_APB2_PRESCALER));

‎drivers/clock_control/clock_stm32_ll_wba.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -67,7 +67,7 @@ static inline int stm32_clock_control_on(const struct device *dev,
6767
ARG_UNUSED(dev);
6868

6969
if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
70-
/* Attemp to toggle a wrong periph clock bit */
70+
/* Attempt to toggle a wrong periph clock bit */
7171
return -ENOTSUP;
7272
}
7373

@@ -88,7 +88,7 @@ static inline int stm32_clock_control_off(const struct device *dev,
8888
ARG_UNUSED(dev);
8989

9090
if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
91-
/* Attemp to toggle a wrong periph clock bit */
91+
/* Attempt to toggle a wrong periph clock bit */
9292
return -ENOTSUP;
9393
}
9494

@@ -487,7 +487,7 @@ static void set_up_fixed_clock_sources(void)
487487
/* Wait for LSE ready */
488488
}
489489

490-
/* Enable LSESYS additionnally */
490+
/* Enable LSESYS additionally */
491491
LL_RCC_LSE_EnablePropagation();
492492
/* Wait till LSESYS is ready */
493493
while (!LL_RCC_LSE_IsPropagationReady()) {

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