| 
 | 1 | +.. _nucleo_wb55rg_board:  | 
 | 2 | + | 
 | 3 | +ST Nucleo WB55RG  | 
 | 4 | +################  | 
 | 5 | + | 
 | 6 | +Overview  | 
 | 7 | +********  | 
 | 8 | + | 
 | 9 | +The Nucleo WB55RG board is a multi-protocol wireless and ultra-low-power device  | 
 | 10 | +embedding a powerful and ultra-low-power radio compliant with the Bluetooth®  | 
 | 11 | +Low Energy (BLE) SIG specification v5.0 and with IEEE 802.15.4-2011.  | 
 | 12 | + | 
 | 13 | + | 
 | 14 | +- STM32 microcontroller in VFQFPN68 package  | 
 | 15 | +- 2.4 GHz RF transceiver supporting Bluetooth® specification v5.0 and  | 
 | 16 | +  IEEE 802.15.4-2011 PHY and MAC  | 
 | 17 | +- Dedicated Arm® 32-bit Cortex® M0+ CPU for real-time Radio layer  | 
 | 18 | +- Three user LEDs  | 
 | 19 | +- Board connector: USB user with Micro-B  | 
 | 20 | +- Two types of extension resources:  | 
 | 21 | + | 
 | 22 | +  - Arduino Uno V3 connectivity  | 
 | 23 | +  - ST morpho extension pin headers for full access to all STM32 I/Os  | 
 | 24 | + | 
 | 25 | +- Integrated PCB antenna or footprint for SMA connector  | 
 | 26 | +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector  | 
 | 27 | +- Flexible power-supply options: ST-LINK USB VBUS or external sources  | 
 | 28 | +- On-board socket for CR2032 battery  | 
 | 29 | +- On-board ST-LINK/V2-1 debugger/programmer with USB re- enumeration capability:  | 
 | 30 | +  mass storage, virtual COM port and debug port  | 
 | 31 | + | 
 | 32 | +.. image:: img/nucleowb55rg.jpg  | 
 | 33 | +   :width: 670px  | 
 | 34 | +   :align: center  | 
 | 35 | +   :height: 339px  | 
 | 36 | +   :alt: Nucleo WB55RG  | 
 | 37 | + | 
 | 38 | +More information about the board can be found at the `Nucleo WB55RG website`_.  | 
 | 39 | + | 
 | 40 | +Hardware  | 
 | 41 | +********  | 
 | 42 | + | 
 | 43 | +STM32WB55RG is an ultra-low-power dual core Arm Cortex-M4 MCU 64 MHz,Cortex-M0 32MHz  | 
 | 44 | +with 1 Mbyte of Flash memory, Bluetooth 5, 802.15.4, USB, LCD, AES-256 SoC and  | 
 | 45 | +provides the following hardware capabilities:  | 
 | 46 | + | 
 | 47 | +- Ultra-low-power with FlexPowerControl (down to 600 nA Standby mode with RTC and 32KB RAM)  | 
 | 48 | +- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 64 MHz  | 
 | 49 | +- Radio:  | 
 | 50 | + | 
 | 51 | +  - 2.4GHz  | 
 | 52 | +  - RF transceiver supporting Bluetooth® 5 specification, IEEE 802.15.4-2011 PHY and MAC,  | 
 | 53 | +    supporting Thread and ZigBee|reg| 3.0  | 
 | 54 | +  - RX Sensitivity: -96 dBm (Bluetooth|reg| Low Energy at 1 Mbps), -100 dBm (802.15.4)  | 
 | 55 | +  - Programmable output power up to +6 dBm with 1 dB steps  | 
 | 56 | +  - Integrated balun to reduce BOM  | 
 | 57 | +  - Support for 2 Mbps  | 
 | 58 | +  - Dedicated Arm|reg| 32-bit Cortex|reg| M0 + CPU for real-time Radio layer  | 
 | 59 | +  - Accurate RSSI to enable power control  | 
 | 60 | +  - Suitable for systems requiring compliance with radio frequency regulations  | 
 | 61 | +    ETSI EN 300 328, EN 300 440, FCC CFR47 Part 15 and ARIB STD-T66  | 
 | 62 | +  - Support for external PA  | 
 | 63 | + | 
 | 64 | +- Clock Sources:  | 
 | 65 | + | 
 | 66 | +  - 32 MHz crystal oscillator with integrated trimming capacitors (Radio and CPU clock)  | 
 | 67 | +  - 32 kHz crystal oscillator for RTC (LSE)  | 
 | 68 | +  - 2x Internal low-power 32 kHz RC (|plusminus| 5% and |plusminus| 500ppm)  | 
 | 69 | +  - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by  | 
 | 70 | +    LSE (better than  |plusminus| 0.25 % accuracy)  | 
 | 71 | +  - 2 PLLs for system clock, USB, SAI and ADC  | 
 | 72 | + | 
 | 73 | +- RTC with HW calendar, alarms and calibration  | 
 | 74 | +- LCD 8 x 40 or 4 x 44 with step-up converter  | 
 | 75 | +- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors  | 
 | 76 | +- 16x timers:  | 
 | 77 | + | 
 | 78 | +  - 2x 16-bit advanced motor-control  | 
 | 79 | +  - 2x 32-bit and 5x 16-bit general purpose  | 
 | 80 | +  - 2x 16-bit basic  | 
 | 81 | +  - 2x low-power 16-bit timers (available in Stop mode)  | 
 | 82 | +  - 2x watchdogs  | 
 | 83 | +  - SysTick timer  | 
 | 84 | + | 
 | 85 | +- Up to 114 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V  | 
 | 86 | +- Memories  | 
 | 87 | + | 
 | 88 | +  - Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection  | 
 | 89 | +  - Up to 320 KB of SRAM including 64 KB with hardware parity check  | 
 | 90 | +  - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories  | 
 | 91 | +  - Quad SPI memory interface  | 
 | 92 | + | 
 | 93 | +- 4x digital filters for sigma delta modulator  | 
 | 94 | +- Rich analog peripherals (down to 1.62 V)  | 
 | 95 | + | 
 | 96 | +  - 12-bit ADC 4.26Msps, up to 16-bit with hardware oversampling, 200 uA/Msps  | 
 | 97 | +  - 2x ultra-low-power comparator  | 
 | 98 | +  - Accurate 2.5 V or 2.048 V reference voltage buffered output  | 
 | 99 | + | 
 | 100 | +- System peripherals  | 
 | 101 | + | 
 | 102 | +  - Inter processor communication controller (IPCC) for communication with  | 
 | 103 | +    Bluetooth|reg| Low Energy and 802.15.4  | 
 | 104 | +  - HW semaphores for resources sharing between CPUs  | 
 | 105 | +  - 2x DMA controllers (7x channels each) supporting ADC, SPI, I2C, USART,  | 
 | 106 | +    QSPI, SAI, AES, Timers  | 
 | 107 | +  - 1x USART (ISO 7816, IrDA, SPI Master, Modbus and Smartcard mode)  | 
 | 108 | +  - 1x LPUART (low power)  | 
 | 109 | +  - 2x SPI 32 Mbit/s  | 
 | 110 | +  - 2x I2C (SMBus/PMBus)  | 
 | 111 | +  - 1x SAI (dual channel high quality audio)  | 
 | 112 | +  - 1x USB 2.0 FS device, crystal-less, BCD and LPM  | 
 | 113 | +  - Touch sensing controller, up to 18 sensors  | 
 | 114 | +  - LCD 8x40 with step-up converter  | 
 | 115 | +  - 1x 16-bit, four channels advanced timer  | 
 | 116 | +  - 2x 16-bits, two channels timer  | 
 | 117 | +  - 1x 32-bits, four channels timer  | 
 | 118 | +  - 2x 16-bits ultra-low-power timer  | 
 | 119 | +  - 1x independent Systick  | 
 | 120 | +  - 1x independent watchdog  | 
 | 121 | +  - 1x window watchdog  | 
 | 122 | + | 
 | 123 | +- Security and ID  | 
 | 124 | + | 
 | 125 | + - 3x hardware encryption AES maximum 256-bit for the application,  | 
 | 126 | +   the Bluetooth|reg| Low Energy and IEEE802.15.4  | 
 | 127 | + - Customer key storage / key manager services  | 
 | 128 | + - HW public key authority (PKA)  | 
 | 129 | + - Cryptographic algorithms: RSA, Diffie-Helman, ECC over GF(p)  | 
 | 130 | + - True random number generator (RNG)  | 
 | 131 | + - Sector protection against R/W operation (PCROP)  | 
 | 132 | + - CRC calculation unit  | 
 | 133 | + - 96-bit unique ID  | 
 | 134 | + - 64-bit unique ID. Possibility to derive 802.15.5 64-bit and  | 
 | 135 | +   Bluetooth|reg| Low Energy 48-bit EUI  | 
 | 136 | + | 
 | 137 | +- Up to 72 fast I/Os, 70 of them 5 V-tolerant  | 
 | 138 | +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade|  | 
 | 139 | + | 
 | 140 | + | 
 | 141 | +More information about STM32WB55RG can be found here:  | 
 | 142 | + | 
 | 143 | +- `STM32WB55RG on www.st.com`_  | 
 | 144 | +- `STM32WB5RG datasheet`_  | 
 | 145 | + | 
 | 146 | +Supported Features  | 
 | 147 | +==================  | 
 | 148 | + | 
 | 149 | +The Zephyr nucleo_wb55rg board configuration supports the following hardware features:  | 
 | 150 | + | 
 | 151 | ++-----------+------------+-------------------------------------+  | 
 | 152 | +| Interface | Controller | Driver/Component                    |  | 
 | 153 | ++===========+============+=====================================+  | 
 | 154 | +| NVIC      | on-chip    | nested vector interrupt controller  |  | 
 | 155 | ++-----------+------------+-------------------------------------+  | 
 | 156 | +| UART      | on-chip    | serial port-polling;                |  | 
 | 157 | +|           |            | serial port-interrupt               |  | 
 | 158 | ++-----------+------------+-------------------------------------+  | 
 | 159 | +| PINMUX    | on-chip    | pinmux                              |  | 
 | 160 | ++-----------+------------+-------------------------------------+  | 
 | 161 | +| GPIO      | on-chip    | gpio                                |  | 
 | 162 | ++-----------+------------+-------------------------------------+  | 
 | 163 | + | 
 | 164 | +Other hardware features are not yet supported on this Zephyr port.  | 
 | 165 | + | 
 | 166 | +The default configuration can be found in the defconfig file:  | 
 | 167 | +``boards/arm/nucleo_wb55rg/nucleo_wb55rg_defconfig``  | 
 | 168 | + | 
 | 169 | + | 
 | 170 | +Connections and IOs  | 
 | 171 | +===================  | 
 | 172 | + | 
 | 173 | +Nucleo WB55RG Board has 6 GPIO controllers. These controllers are responsible for pin muxing,  | 
 | 174 | +input/output, pull-up, etc.  | 
 | 175 | + | 
 | 176 | +Default Zephyr Peripheral Mapping:  | 
 | 177 | +----------------------------------  | 
 | 178 | + | 
 | 179 | +- UART_1 TX/RX : PB7/PB6  | 
 | 180 | +- USER_PB : PC4  | 
 | 181 | +- USER_PB1 : PD0  | 
 | 182 | +- USER_PB2 : PD1  | 
 | 183 | +- LD1 : PB5  | 
 | 184 | +- LD2 : PB0  | 
 | 185 | +- LD3 : PB1  | 
 | 186 | + | 
 | 187 | +System Clock  | 
 | 188 | +------------  | 
 | 189 | + | 
 | 190 | +Nucleo WB55RG System Clock could be driven by internal or external oscillator,  | 
 | 191 | +as well as main PLL clock. By default System clock is driven by HSE clock at 32MHz.  | 
 | 192 | + | 
 | 193 | +Serial Port  | 
 | 194 | +-----------  | 
 | 195 | + | 
 | 196 | +Nucleo WB55RG board has 2 (LP)U(S)ARTs. The Zephyr console output is assigned to USART1.  | 
 | 197 | +Default settings are 115200 8N1.  | 
 | 198 | + | 
 | 199 | + | 
 | 200 | +Programming and Debugging  | 
 | 201 | +*************************  | 
 | 202 | + | 
 | 203 | +Applications for the ``nucleo_wb55rg`` board configuration can be built the  | 
 | 204 | +usual way (see :ref:`build_an_application`).  | 
 | 205 | + | 
 | 206 | +Flashing  | 
 | 207 | +========  | 
 | 208 | + | 
 | 209 | +Nucleo WB55RG board includes an ST-LINK/V2-1 embedded debug tool  | 
 | 210 | +interface.  This interface is not yet supported by the openocd version  | 
 | 211 | +included in the Zephyr SDK. You can flash your application with drag and drop  | 
 | 212 | +in the drive mounted when plugging your nucleo board to your PC.  | 
 | 213 | + | 
 | 214 | + | 
 | 215 | +Flashing an application to Nucleo WB55RG  | 
 | 216 | +----------------------------------------  | 
 | 217 | + | 
 | 218 | +Connect the Nucleo WB55RG to your host computer using the USB port.  | 
 | 219 | +Then build and flash an application. Here is an example for the  | 
 | 220 | +:ref:`hello_world` application.  | 
 | 221 | + | 
 | 222 | +Run a serial host program to connect with your Nucleo board:  | 
 | 223 | + | 
 | 224 | +.. code-block:: console  | 
 | 225 | +
  | 
 | 226 | +   $ minicom -D /dev/ttyUSB0  | 
 | 227 | +
  | 
 | 228 | +Then build and flash the application.  | 
 | 229 | + | 
 | 230 | +.. zephyr-app-commands::  | 
 | 231 | +   :zephyr-app: samples/hello_world  | 
 | 232 | +   :board: nucleo_wb55rg  | 
 | 233 | +   :goals: build  | 
 | 234 | + | 
 | 235 | +You should see the following message on the console:  | 
 | 236 | + | 
 | 237 | +.. code-block:: console  | 
 | 238 | +
  | 
 | 239 | +   Hello World! arm  | 
 | 240 | +
  | 
 | 241 | +Debugging  | 
 | 242 | +=========  | 
 | 243 | + | 
 | 244 | +While STM32WB55RG is not yet supported you can debug an application using pyocd.  | 
 | 245 | +Here is an example for the :ref:`hello_world` application.  | 
 | 246 | +Start pyocd gdbserver on your machine:  | 
 | 247 | + | 
 | 248 | +.. code-block:: console  | 
 | 249 | +
  | 
 | 250 | +   $ pyocd gdbserver  | 
 | 251 | +
  | 
 | 252 | +Then launch debug on your board:  | 
 | 253 | + | 
 | 254 | +.. zephyr-app-commands::  | 
 | 255 | +   :zephyr-app: samples/hello_world  | 
 | 256 | +   :board: nucleo_wb55rg  | 
 | 257 | +   :maybe-skip-config:  | 
 | 258 | +   :goals: debug  | 
 | 259 | + | 
 | 260 | +.. _Nucleo WB55RG website:  | 
 | 261 | +   https://www.st.com/en/evaluation-tools/p-nucleo-wb55.html  | 
 | 262 | + | 
 | 263 | +.. _STM32WB55RG on www.st.com:  | 
 | 264 | +   https://www.st.com/en/microcontrollers-microprocessors/stm32wb55rg.html  | 
 | 265 | + | 
 | 266 | +.. _STM32WB5RG datasheet:  | 
 | 267 | +   https://www.st.com/resource/en/datasheet/stm32wb55rg.pdf  | 
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