Skip to content

Commit 37b24ab

Browse files
soburinashif
soburi
authored and
nashif
committed
driver: clock_control: renesas_ra: Defining MSTP regs in devicetree
Allows MSTP register addresses to be changed in the device tree to support different configuration SoCs. Signed-off-by: TOKITA Hiroshi <[email protected]>
1 parent 6446ce8 commit 37b24ab

File tree

14 files changed

+107
-19
lines changed

14 files changed

+107
-19
lines changed

‎drivers/clock_control/clock_control_renesas_ra_cgc.c‎

Lines changed: 13 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -12,14 +12,25 @@
1212
#include <zephyr/dt-bindings/clock/ra_clock.h>
1313
#include <zephyr/drivers/clock_control/renesas_ra_cgc.h>
1414

15+
#if DT_NODE_HAS_STATUS(DT_NODELABEL(pclkblock), okay)
16+
#define MSTP_REGS_ELEM(node_id, prop, idx) \
17+
[DT_STRING_TOKEN_BY_IDX(node_id, prop, idx)] = \
18+
(volatile uint32_t *)DT_REG_ADDR_BY_IDX(node_id, idx),
19+
20+
static volatile uint32_t *mstp_regs[] = {
21+
DT_FOREACH_PROP_ELEM(DT_NODELABEL(pclkblock), reg_names, MSTP_REGS_ELEM)};
22+
#else
23+
static volatile uint32_t *mstp_regs[] = {};
24+
#endif
25+
1526
static int clock_control_renesas_ra_on(const struct device *dev, clock_control_subsys_t sys)
1627
{
1728
struct clock_control_ra_subsys_cfg *subsys_clk = (struct clock_control_ra_subsys_cfg *)sys;
1829

1930
if (!dev || !sys) {
2031
return -EINVAL;
2132
}
22-
WRITE_BIT(*subsys_clk->mstp, subsys_clk->stop_bit, false);
33+
WRITE_BIT(*mstp_regs[subsys_clk->mstp], subsys_clk->stop_bit, false);
2334
return 0;
2435
}
2536

@@ -31,7 +42,7 @@ static int clock_control_renesas_ra_off(const struct device *dev, clock_control_
3142
return -EINVAL;
3243
}
3344

34-
WRITE_BIT(*subsys_clk->mstp, subsys_clk->stop_bit, true);
45+
WRITE_BIT(*mstp_regs[subsys_clk->mstp], subsys_clk->stop_bit, true);
3546
return 0;
3647
}
3748

‎dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,9 @@
2222
};
2323

2424
clocks: clocks {
25+
#address-cells = <1>;
26+
#size-cells = <1>;
27+
2528
xtal: clock-xtal {
2629
compatible = "renesas,ra-cgc-external-clock";
2730
clock-frequency = <DT_FREQ_M(12)>;
@@ -54,8 +57,12 @@
5457
status = "disabled";
5558
};
5659

57-
pclkblock: pclkblock {
60+
pclkblock: pclkblock@4001e01c {
5861
compatible = "renesas,ra-cgc-pclk-block";
62+
reg = <0x4001e01c 4>, <0x40047000 4>, <0x40047004 4>,
63+
<0x40047008 4>;
64+
reg-names = "MSTPA", "MSTPB","MSTPC",
65+
"MSTPD";
5966
#clock-cells = <0>;
6067
sysclock-src = <RA_CLOCK_SOURCE_HOCO>;
6168
status = "okay";

‎dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -92,6 +92,9 @@
9292
};
9393

9494
clocks: clocks {
95+
#address-cells = <1>;
96+
#size-cells = <1>;
97+
9598
xtal: clock-xtal {
9699
compatible = "renesas,ra-cgc-external-clock";
97100
clock-frequency = <DT_FREQ_M(20)>;
@@ -146,8 +149,12 @@
146149
status = "disabled";
147150
};
148151

149-
pclkblock: pclkblock {
152+
pclkblock: pclkblock@40084000 {
150153
compatible = "renesas,ra-cgc-pclk-block";
154+
reg = <0x40084000 4>, <0x40084004 4>, <0x40084008 4>,
155+
<0x4008400c 4>, <0x40084010 4>;
156+
reg-names = "MSTPA", "MSTPB","MSTPC",
157+
"MSTPD", "MSTPE";
151158
#clock-cells = <0>;
152159
sysclock-src = <RA_CLOCK_SOURCE_PLL>;
153160
status = "okay";

‎dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,9 @@
3333
};
3434

3535
clocks: clocks {
36+
#address-cells = <1>;
37+
#size-cells = <1>;
38+
3639
xtal: clock-xtal {
3740
compatible = "renesas,ra-cgc-external-clock";
3841
clock-frequency = <DT_FREQ_M(20)>;
@@ -76,8 +79,12 @@
7679
status = "disabled";
7780
};
7881

79-
pclkblock: pclkblock {
82+
pclkblock: pclkblock@40084000 {
8083
compatible = "renesas,ra-cgc-pclk-block";
84+
reg = <0x40084000 4>, <0x40084004 4>, <0x40084008 4>,
85+
<0x4008400c 4>, <0x40084010 4>;
86+
reg-names = "MSTPA", "MSTPB","MSTPC",
87+
"MSTPD", "MSTPE";
8188
#clock-cells = <0>;
8289
sysclock-src = <RA_CLOCK_SOURCE_PLL>;
8390
status = "okay";

‎dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,9 @@
2727
};
2828

2929
clocks: clocks {
30+
#address-cells = <1>;
31+
#size-cells = <1>;
32+
3033
xtal: clock-xtal {
3134
compatible = "renesas,ra-cgc-external-clock";
3235
clock-frequency = <DT_FREQ_M(12)>;
@@ -70,8 +73,12 @@
7073
status = "disabled";
7174
};
7275

73-
pclkblock: pclkblock {
76+
pclkblock: pclkblock@4001e01c {
7477
compatible = "renesas,ra-cgc-pclk-block";
78+
reg = <0x4001e01c 4>, <0x40047000 4>, <0x40047004 4>,
79+
<0x40047008 4>;
80+
reg-names = "MSTPA", "MSTPB","MSTPC",
81+
"MSTPD";
7582
#clock-cells = <0>;
7683
sysclock-src = <RA_CLOCK_SOURCE_PLL>;
7784
status = "okay";

‎dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -58,6 +58,9 @@
5858
};
5959

6060
clocks: clocks {
61+
#address-cells = <1>;
62+
#size-cells = <1>;
63+
6164
xtal: clock-xtal {
6265
compatible = "renesas,ra-cgc-external-clock";
6366
clock-frequency = <DT_FREQ_M(12)>;
@@ -101,8 +104,12 @@
101104
status = "disabled";
102105
};
103106

104-
pclkblock: pclkblock {
107+
pclkblock: pclkblock@4001e01c {
105108
compatible = "renesas,ra-cgc-pclk-block";
109+
reg = <0x4001e01c 4>, <0x40047000 4>, <0x40047004 4>,
110+
<0x40047008 4>;
111+
reg-names = "MSTPA", "MSTPB","MSTPC",
112+
"MSTPD";
106113
#clock-cells = <0>;
107114
sysclock-src = <RA_CLOCK_SOURCE_PLL>;
108115
status = "okay";

‎dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -98,6 +98,9 @@
9898
};
9999

100100
clocks: clocks {
101+
#address-cells = <1>;
102+
#size-cells = <1>;
103+
101104
xtal: clock-xtal {
102105
compatible = "renesas,ra-cgc-external-clock";
103106
clock-frequency = <DT_FREQ_M(24)>;
@@ -141,8 +144,12 @@
141144
status = "disabled";
142145
};
143146

144-
pclkblock: pclkblock {
147+
pclkblock: pclkblock@4001e01c {
145148
compatible = "renesas,ra-cgc-pclk-block";
149+
reg = <0x4001e01c 4>, <0x40047000 4>, <0x40047004 4>,
150+
<0x40047008 4>;
151+
reg-names = "MSTPA", "MSTPB","MSTPC",
152+
"MSTPD";
146153
#clock-cells = <0>;
147154
sysclock-src = <RA_CLOCK_SOURCE_PLL>;
148155
status = "okay";

‎dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -128,6 +128,9 @@
128128
};
129129

130130
clocks: clocks {
131+
#address-cells = <1>;
132+
#size-cells = <1>;
133+
131134
xtal: clock-xtal {
132135
compatible = "renesas,ra-cgc-external-clock";
133136
clock-frequency = <DT_FREQ_M(24)>;
@@ -182,8 +185,12 @@
182185
status = "disabled";
183186
};
184187

185-
pclkblock: pclkblock {
188+
pclkblock: pclkblock@40084000 {
186189
compatible = "renesas,ra-cgc-pclk-block";
190+
reg = <0x40084000 4>, <0x40084004 4>, <0x40084008 4>,
191+
<0x4008400c 4>, <0x40084010 4>;
192+
reg-names = "MSTPA", "MSTPB","MSTPC",
193+
"MSTPD", "MSTPE";
187194
#clock-cells = <0>;
188195
sysclock-src = <RA_CLOCK_SOURCE_PLL>;
189196
status = "okay";

‎dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -188,6 +188,9 @@
188188
};
189189

190190
clocks: clocks {
191+
#address-cells = <1>;
192+
#size-cells = <1>;
193+
191194
xtal: clock-xtal {
192195
compatible = "renesas,ra-cgc-external-clock";
193196
clock-frequency = <DT_FREQ_M(24)>;
@@ -242,8 +245,12 @@
242245
status = "disabled";
243246
};
244247

245-
pclkblock: pclkblock {
248+
pclkblock: pclkblock@40084000 {
246249
compatible = "renesas,ra-cgc-pclk-block";
250+
reg = <0x40084000 4>, <0x40084004 4>, <0x40084008 4>,
251+
<0x4008400c 4>, <0x40084010 4>;
252+
reg-names = "MSTPA", "MSTPB","MSTPC",
253+
"MSTPD", "MSTPE";
247254
#clock-cells = <0>;
248255
sysclock-src = <RA_CLOCK_SOURCE_PLL>;
249256
status = "okay";

‎dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,9 @@
99

1010
/ {
1111
clocks: clocks {
12+
#address-cells = <1>;
13+
#size-cells = <1>;
14+
1215
xtal: clock-xtal {
1316
compatible = "renesas,ra-cgc-external-clock";
1417
clock-frequency = <DT_FREQ_M(20)>;
@@ -75,8 +78,12 @@
7578
status = "disabled";
7679
};
7780

78-
pclkblock: pclkblock {
81+
pclkblock: pclkblock@40203000 {
7982
compatible = "renesas,ra-cgc-pclk-block";
83+
reg = <0x40203000 4>, <0x40203004 4>, <0x40203008 4>,
84+
<0x4020300c 4>, <0x40203010 4>;
85+
reg-names = "MSTPA", "MSTPB","MSTPC",
86+
"MSTPD", "MSTPE";
8087
#clock-cells = <0>;
8188
sysclock-src = <RA_CLOCK_SOURCE_PLL1P>;
8289
status = "okay";

0 commit comments

Comments
 (0)