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boards: lpcxpresso55s69: Add I2S support
Add I2S support for LPCXpresso55S69 board Signed-off-by: Mahesh Mahadevan <[email protected]>
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‎boards/arm/lpcxpresso55s69/doc/index.rst‎

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@@ -84,6 +84,8 @@ features:
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+-----------+------------+-------------------------------------+
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| COUNTER | on-chip | counter |
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+-----------+------------+-------------------------------------+
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| I2S | on-chip | i2s |
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+-----------+------------+-------------------------------------+
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Targets available
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==================
@@ -143,6 +145,14 @@ functionality of a pin.
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+---------+-----------------+----------------------------+
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| PIO1_24 | USART | USART RX |
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+---------+-----------------+----------------------------+
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| PIO0_20 | I2S | I2S DATAOUT |
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+---------+-----------------+----------------------------+
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| PIO0_19 | I2S | I2S TX WS |
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+---------+-----------------+----------------------------+
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| PIO0_21 | I2S | I2S TX SCK |
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+---------+-----------------+----------------------------+
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| PIO1_13 | I2S | I2S DATAIN |
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+---------+-----------------+----------------------------+
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Memory mappings
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===============

‎boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu0.dts‎

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@@ -129,3 +129,25 @@ zephyr_udc0: &usbhs {
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&ctimer4 {
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status = "okay";
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};
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/* I2S receive channel */
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i2s0: &flexcomm6 {
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status = "okay";
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compatible = "nxp,lpc-i2s";
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label = "I2S_0";
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#address-cells = <1>;
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#size-cells = <0>;
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dmas = <&dma0 16>;
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dma-names = "rx";
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};
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/* I2S transmit channel */
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i2s1: &flexcomm7 {
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status = "okay";
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compatible = "nxp,lpc-i2s";
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label = "I2S_1";
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#address-cells = <1>;
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#size-cells = <0>;
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dmas = <&dma0 19>;
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dma-names = "tx";
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};

‎boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu0.yaml‎

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@@ -22,6 +22,7 @@ supported:
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- counter
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- gpio
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- i2c
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- i2s
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- spi
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- usb_device
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- watchdog

‎boards/arm/lpcxpresso55s69/pinmux.c‎

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@@ -183,6 +183,70 @@ static int lpcxpresso_55s69_pinmux_init(const struct device *dev)
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IOCON_PIO_OPENDRAIN_DI);
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#endif
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#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm6), nxp_lpc_i2s, okay)) && \
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(DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm7), nxp_lpc_i2s, okay)) && \
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CONFIG_I2S
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CLOCK_EnableClock(kCLOCK_Sysctl);
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/* Set shared signal set 0 SCK, WS from Transmit I2S - Flexcomm 7 */
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SYSCTL->SHAREDCTRLSET[0] = SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL(7) |
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SYSCTL_SHAREDCTRLSET_SHAREDWSSEL(7);
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#ifdef CONFIG_I2S_TEST_SEPARATE_DEVICES
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/* Select Data in from Transmit I2S - Flexcomm 7 */
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SYSCTL->SHAREDCTRLSET[0] |= SYSCTL_SHAREDCTRLSET_SHAREDDATASEL(7);
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/* Enable Transmit I2S - Flexcomm 7 for Shared Data Out */
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SYSCTL->SHAREDCTRLSET[0] |= SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN(1);
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#endif
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/* Set Receive I2S - Flexcomm 6 SCK, WS from shared signal set 0 */
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SYSCTL->FCCTRLSEL[6] = SYSCTL_FCCTRLSEL_SCKINSEL(1) |
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SYSCTL_FCCTRLSEL_WSINSEL(1);
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/* Set Transmit I2S - Flexcomm 7 SCK, WS from shared signal set 0 */
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SYSCTL->FCCTRLSEL[7] = SYSCTL_FCCTRLSEL_SCKINSEL(1) |
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SYSCTL_FCCTRLSEL_WSINSEL(1);
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#ifdef CONFIG_I2S_TEST_SEPARATE_DEVICES
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/* Select Receive I2S - Flexcomm 6 Data in from shared signal set 0 */
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SYSCTL->FCCTRLSEL[6] |= SYSCTL_FCCTRLSEL_DATAINSEL(1);
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/* Select Transmit I2S - Flexcomm 7 Data out to shared signal set 0 */
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SYSCTL->FCCTRLSEL[7] |= SYSCTL_FCCTRLSEL_DATAOUTSEL(1);
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#endif
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/* Pin is configured as FC7_TXD_SCL_MISO_WS */
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pinmux_pin_set(port0, 19, IOCON_PIO_FUNC7 |
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IOCON_PIO_MODE_PULLUP |
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IOCON_PIO_SLEW_FAST |
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IOCON_PIO_INV_DI |
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IOCON_PIO_DIGITAL_EN |
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IOCON_PIO_OPENDRAIN_DI);
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/* Pin is configured as FC7_RXD_SDA_MOSI_DATA */
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pinmux_pin_set(port0, 20, IOCON_PIO_FUNC7 |
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IOCON_PIO_MODE_PULLUP |
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IOCON_PIO_SLEW_FAST |
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IOCON_PIO_INV_DI |
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IOCON_PIO_DIGITAL_EN |
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IOCON_PIO_OPENDRAIN_DI);
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/* Pin is configured as FC7_SCK */
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pinmux_pin_set(port0, 21, IOCON_PIO_FUNC7 |
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IOCON_PIO_MODE_PULLUP |
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IOCON_PIO_SLEW_FAST |
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IOCON_PIO_INV_DI |
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IOCON_PIO_DIGITAL_EN |
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IOCON_PIO_OPENDRAIN_DI);
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/* Pin is configured as FC6_RXD_SDA_MOSI_DATA */
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pinmux_pin_set(port1, 13, IOCON_PIO_FUNC2 |
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IOCON_PIO_MODE_PULLUP |
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IOCON_PIO_SLEW_FAST |
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IOCON_PIO_INV_DI |
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IOCON_PIO_DIGITAL_EN |
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IOCON_PIO_OPENDRAIN_DI);
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#endif
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return 0;
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}
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‎soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S69_cpu0‎

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@@ -49,4 +49,9 @@ config COUNTER_MCUX_CTIMER
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default y
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depends on COUNTER
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config I2S_MCUX_FLEXCOMM
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default y if HAS_MCUX_FLEXCOMM
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depends on I2S
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select INIT_PLL0
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endif # SOC_LPC55S69_CPU0

‎soc/arm/nxp_lpc/lpc55xxx/Kconfig.soc‎

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@@ -77,6 +77,9 @@ config SOC_PART_NUMBER_LPC55XXX
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option that you should not set directly. The part number selection
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choice defines the default value for this string.
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config INIT_PLL0
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bool "Initialize PLL0"
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config SECOND_CORE_MCUX
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bool "Enable LPC55xxx's second core"
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depends on HAS_MCUX

‎soc/arm/nxp_lpc/lpc55xxx/soc.c‎

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@@ -36,6 +36,18 @@
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#define TO_CLOCK_ATTACH_ID(inst, val) MUX_A(CM_CTIMERCLKSEL##inst, val)
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#define CTIMER_CLOCK_SETUP(node_id) CLOCK_AttachClk(CTIMER_CLOCK_SOURCE(node_id));
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#ifdef CONFIG_INIT_PLL0
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const pll_setup_t pll0Setup = {
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.pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(2U) |
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SYSCON_PLL0CTRL_SELP(31U),
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.pllndec = SYSCON_PLL0NDEC_NDIV(125U),
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.pllpdec = SYSCON_PLL0PDEC_PDIV(8U),
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.pllsscg = {0x0U, (SYSCON_PLL0SSCG1_MDIV_EXT(3072U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
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.pllRate = 24576000U,
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.flags = PLL_SETUPFLAG_WAITLOCK}
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;
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#endif
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/**
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*
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* @brief Initialize the system clock
@@ -60,6 +72,25 @@ static ALWAYS_INLINE void clock_init(void)
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/* Enable FRO HF(96MHz) output */
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CLOCK_SetupFROClocking(96000000U);
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#ifdef CONFIG_INIT_PLL0
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/*!< Ensure XTAL16M is on */
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PMC->PDRUNCFGCLR0 |= PMC_PDRUNCFG0_PDEN_XTAL32M_MASK;
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PMC->PDRUNCFGCLR0 |= PMC_PDRUNCFG0_PDEN_LDOXO32M_MASK;
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/*!< Ensure CLK_IN is on */
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SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;
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ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;
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/*!< Switch PLL0 clock source selector to XTAL16M */
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CLOCK_AttachClk(kEXT_CLK_to_PLL0);
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/*!< Configure PLL to the desired values */
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CLOCK_SetPLL0Freq(&pll0Setup);
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CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 0U, true);
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CLOCK_SetClkDiv(kCLOCK_DivPll0Clk, 1U, false);
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#endif
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#if !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE)
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/*!< Set FLASH wait states for core */
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CLOCK_SetFLASHAccessCyclesForFreq(96000000U);
@@ -132,6 +163,16 @@ static ALWAYS_INLINE void clock_init(void)
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DT_FOREACH_STATUS_OKAY(nxp_lpc_ctimer, CTIMER_CLOCK_SETUP)
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#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm6), nxp_lpc_i2s, okay))
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/* attach PLL0 clock to FLEXCOMM6 */
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CLOCK_AttachClk(kPLL0_DIV_to_FLEXCOMM6);
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#endif
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#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm7), nxp_lpc_i2s, okay))
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/* attach PLL0 clock to FLEXCOMM6 */
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CLOCK_AttachClk(kPLL0_DIV_to_FLEXCOMM7);
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#endif
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#endif /* CONFIG_SOC_LPC55S69_CPU0 */
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}
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‎soc/arm/nxp_lpc/lpc55xxx/soc.h‎

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@@ -27,14 +27,17 @@
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#define IOCON_PIO_DIGITAL_EN 0x0100u /*!<@brief Enables digital function */
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#define IOCON_PIO_FUNC0 0x00u /*!<@brief Selects pin function 0 */
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#define IOCON_PIO_FUNC1 0x01u /*!<@brief Selects pin function 1 */
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#define IOCON_PIO_FUNC2 0x02u /*!<@brief Selects pin function 1 */
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#define IOCON_PIO_FUNC5 0x05u /*!<@brief Selects pin function 5 */
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#define IOCON_PIO_FUNC7 0x07u /*!<@brief Selects pin function 5 */
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#define IOCON_PIO_FUNC6 0x06u /*!<@brief Selects pin function 6 */
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#define IOCON_PIO_FUNC9 0x09u /*!<@brief Selects pin function 9 */
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#define IOCON_PIO_FUNC10 0x0Au /*!<@brief Selects pin function 10 */
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#define IOCON_PIO_INV_DI 0x00u /*!<@brief Input function not inverted */
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#define IOCON_PIO_MODE_INACT 0x00u /*!<@brief No addition pin function */
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#define IOCON_PIO_OPENDRAIN_DI 0x00u /*!<@brief Open drain is disabled */
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#define IOCON_PIO_SLEW_STANDARD 0x00u /*!<@brief Standard slew rate mode */
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#define IOCON_PIO_SLEW_FAST 0x40u /*!<@brief Fast slew rate mode */
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#define IOCON_PIO_MODE_PULLDOWN 0x10u /*!<@brief Selects pull-down function */
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#define IOCON_PIO_MODE_PULLUP 0x20u /*!<@brief Selects pull-up function */
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#define IOCON_PIO_INPFILT_OFF 0x1000u /*!<@brief Input filter disabled */

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