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soc: kb1200 soc
Add support for ENE KB1200 SOC Signed-off-by: Steven Chang <[email protected]>
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‎soc/ene/kb1200/CMakeLists.txt

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# Copyright (c) 2023 ENE Technology Inc.
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# SPDX-License-Identifier: Apache-2.0
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zephyr_library()
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zephyr_library_sources(soc.c)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

‎soc/ene/kb1200/Kconfig

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# Copyright (c) 2024 ENE Technology Inc.
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# SPDX-License-Identifier: Apache-2.0
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config SOC_KB1200
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select ARM
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select CPU_CORTEX_M4
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select CPU_HAS_ARM_MPU
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_FPU

‎soc/ene/kb1200/Kconfig.defconfig

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# Copyright (c) 2023 ENE Technology Inc.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_KB1200
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config NUM_IRQS
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default 64
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
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config BUILD_OUTPUT_BIN
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default y
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config BUILD_OUTPUT_HEX
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default y
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endif # SOC_KB1200

‎soc/ene/kb1200/Kconfig.soc

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# Copyright (c) 2024 ENE Technology Inc.
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# SPDX-License-Identifier: Apache-2.0
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config SOC_KB1200
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bool
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help
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ENE KB1200
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config SOC
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default "kb1200" if SOC_KB1200

‎soc/ene/kb1200/reg/adc.h

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/*
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* Copyright (c) 2024 ENE Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ENE_KB1200_ADC_H
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#define ENE_KB1200_ADC_H
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/**
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* Structure type to access Analog to Digital Converter (ADC).
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*/
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struct adc_regs {
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volatile uint32_t ADCCFG; /* Configuration Register */
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volatile uint32_t Reserved[3]; /* Reserved */
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volatile uint32_t ADCDAT[14]; /* Data Register */
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};
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#define ADC_CHANNEL_BIT_POS 16
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#define ADC_CHANNEL_BIT_MASK 0x3FFF0000
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#define ADC_RESOLUTION 10 /* Unit:bits */
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#define ADC_VREF_ANALOG 3300 /* Unit:mV */
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#define ADC_MAX_CHAN 14
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#define ADC_FUNCTION_ENABLE 0x0001
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#define ADC_INVALID_VALUE 0x8000
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#define ADC_WAIT_TIME 100
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#define ADC_WAIT_CNT 100
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#endif /* ENE_KB1200_ADDA_H */

‎soc/ene/kb1200/reg/fsmbm.h

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/*
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* Copyright (c) 2024 ENE Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ENE_KB1200_FSMBM_H
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#define ENE_KB1200_FSMBM_H
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/**
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* Structure type to access Flexible SMBus Master (FSMBM).
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*/
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struct fsmbm_regs {
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volatile uint32_t FSMBMCFG; /* Configuration Register */
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volatile uint8_t FSMBMIE; /* Interrupt Enable Register */
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volatile uint8_t Reserved0[3];
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volatile uint8_t FSMBMPF; /* Event Pending Flag Register */
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volatile uint8_t Reserved1[3];
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volatile uint8_t FSMBMFRT; /* Protocol Control Register */
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volatile uint8_t Reserved2[3];
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volatile uint16_t FSMBMPEC; /* PEC Value Register */
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volatile uint16_t Reserved3;
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volatile uint8_t FSMBMSTS; /* Status Register */
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volatile uint8_t Reserved4[3];
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volatile uint8_t FSMBMADR; /* Slave Address Register */
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volatile uint8_t Reserved5[3];
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volatile uint8_t FSMBMCMD; /* Command Register */
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volatile uint8_t Reserved6[3];
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volatile uint8_t FSMBMDAT[32]; /* Data Register */
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volatile uint8_t FSMBMPRTC_P; /* Protocol Register */
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volatile uint8_t FSMBMPRTC_C; /* Protocol Register */
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volatile uint16_t Reserved7;
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volatile uint8_t FSMBMNADR; /* HostNotify Slave Address Register */
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volatile uint8_t Reserved8[3];
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volatile uint16_t FSMBMNDAT; /* HostNotify Data Register */
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volatile uint16_t Reserved9;
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};
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#define FSMBM_NUM 10
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/* data->state */
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#define STATE_IDLE 0
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#define STATE_SENDING 1
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#define STATE_RECEIVING 2
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#define STATE_COMPLETE 3
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/* PROTOCOL */
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#define FLEXIBLE_PROTOCOL 0x7F
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/* Error code */
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#define FSMBM_NO_ERROR 0x00
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#define FSMBM_DEVICE_ADDR_NO_ACK 0x10
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#define FSMBM_CMD_NO_ACK 0x12
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#define FSMBM_DEVICE_DATA_NO_ACK 0x13
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#define FSMBM_LOST_ARBITRATION 0x17
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#define FSMBM_SMBUS_TIMEOUT 0x18
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#define FSMBM_UNSUPPORTED_PRTC 0x19
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#define FSMBM_SMBUS_BUSY 0x1A
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#define FSMBM_STOP_FAIL 0x1E
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#define FSMBM_PEC_ERROR 0x1F
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/* Packet Form */
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#define ___NONE 0x00
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#define ___STOP 0x01
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#define __PEC_ 0x02
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#define __PEC_STOP 0x03
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#define _CNT__ 0x04
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#define _CNT__STOP 0x05
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#define _CNT_PEC_ 0x06
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#define _CNT_PEC_STOP 0x07
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#define CMD___ 0x08
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#define CMD___STOP 0x09
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#define CMD__PEC_ 0x0A
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#define CMD__PEC_STOP 0x0B
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#define CMD_CNT__ 0x0C
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#define CMD_CNT__STOP 0x0D
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#define CMD_CNT_PEC_ 0x0E
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#define CMD_CNT_PEC_STOP 0x0F
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#define FLEXIBLE_CMD 0x08
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#define FLEXIBLE_CNT 0x04
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#define FLEXIBLE_PEC 0x02
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#define FLEXIBLE_STOP 0x01
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/* HW */
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#define FSMBM_BUFFER_SIZE 0x20
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#define FSMBM_MAXCNT 0xFF
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#define FSMBM_WRITE 0x00
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#define FSMBM_READ 0x01
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/* Clock Setting = 1 / (1u + (1u * N)) ,50% Duty Cycle */
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#define FSMBM_CLK_1M 0x0000
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#define FSMBM_CLK_500K 0x0101
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#define FSMBM_CLK_333K 0x0202
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#define FSMBM_CLK_250K 0x0303
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#define FSMBM_CLK_200K 0x0404
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#define FSMBM_CLK_167K 0x0505
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#define FSMBM_CLK_143K 0x0606
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#define FSMBM_CLK_125K 0x0707
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#define FSMBM_CLK_111K 0x0808
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#define FSMBM_CLK_100K 0x0909
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#define FSMBM_CLK_91K 0x0A0A
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#define FSMBM_CLK_83K 0x0B0B
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#define FSMBM_CLK_71K 0x0D0D
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#define FSMBM_CLK_63K 0x0F0F
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#define FSMBM_CLK_50K 0x1313
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#define FSMBM_CLK_40K 0x1818
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#define FSMBM_CLK_30K 0x2020
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#define FSMBM_CLK_20K 0x3131
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#define FSMBM_CLK_10K 0x6363
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/* Other(non 50% Duty Cycle) */
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#define FSMBM_CLK_400K 0x0102
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#define FSMBM_COMPLETE_EVENT 0x01
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#define FSMBM_HOST_NOTIFY_EVENT 0x02
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#define FSMBM_BLOCK_FINISH_EVENT 0x04
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#define FSMBM_FUNCTION_ENABLE 0x01
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#define FSMBM_TIMEOUT_ENABLE 0x02
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#define FSMBM_HW_RESET 0x10
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#define FSMBM_CLK_POS 16
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#define FSMBM_CLK_MASK 0xFFFF
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#define FSMBM_STS_MASK 0x1F
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#endif /* ENE_KB1200_FSMBM_H */

‎soc/ene/kb1200/reg/gcfg.h

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/*
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* Copyright (c) 2023 ENE Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ENE_KB1200_GCFG_H
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#define ENE_KB1200_GCFG_H
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/**
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* Structure type to access General Configuration (GCFG).
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*/
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struct gcfg_regs {
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volatile uint8_t IDV; /*Version ID Register */
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volatile uint8_t Reserved0; /*Reserved */
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volatile uint16_t IDC; /*Chip ID Register */
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volatile uint32_t FWID; /*Firmware ID Register */
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volatile uint32_t MCURST; /*MCU Reset Control Register */
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volatile uint32_t RSTFLAG; /*Reset Pending Flag Register */
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volatile uint32_t GPIOALT; /*GPIO Alternate Register */
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volatile uint8_t VCCSTA; /*VCC Status Register */
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volatile uint8_t Reserved1[3]; /*Reserved */
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volatile uint16_t GPIOMUX; /*GPIO MUX Control Register */
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volatile uint16_t Reserved2; /*Reserved */
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volatile uint16_t I2CSPMS; /*I2CS Pin Map Selection Register */
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volatile uint16_t Reserved3; /*Reserved */
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volatile uint8_t CLKCFG; /*Clock Configuration Register */
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volatile uint8_t Reserved4[3]; /*Reserved */
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volatile uint32_t DPLLFREQ; /*DPLL Frequency Register */
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volatile uint32_t Reserved5; /*Reserved */
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volatile uint32_t GCFGMISC; /*Misc. Register */
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volatile uint8_t EXTIE; /*Extended Command Interrupt Enable Register */
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volatile uint8_t Reserved6[3]; /*Reserved */
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volatile uint8_t EXTPF; /*Extended Command Pending Flag Register */
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volatile uint8_t Reserved7[3]; /*Reserved */
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volatile uint32_t EXTARG; /*Extended Command Argument0/1/2 Register */
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volatile uint8_t EXTCMD; /*Extended Command Port Register */
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volatile uint8_t Reserved8[3]; /*Reserved */
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volatile uint32_t ADCOTR; /*ADCO Register */
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volatile uint32_t IDSR; /*IDSR Register */
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volatile uint32_t Reserved9[14]; /*Reserved */
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volatile uint32_t TRAPMODE;
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volatile uint32_t CLK1UCFG;
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volatile uint32_t LDO15TRIM;
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volatile uint32_t Reserved10;
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volatile uint32_t WWTR;
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volatile uint32_t ECMISC2;
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volatile uint32_t DPLLCTRL;
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};
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#define GCFG_CLKCFG_96M 0x00000004
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#define GCFG_CLKCFG_48M 0x00000014
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#define GCFG_CLKCFG_24M 0x00000024
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#endif /* ENE_KB1200_GCFG_H */

‎soc/ene/kb1200/reg/gpio.h

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/*
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* Copyright (c) 2023 ENE Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ENE_KB1200_GPIO_H
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#define ENE_KB1200_GPIO_H
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/**
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* Structure type to access General Purpose Input/Output (GPIO).
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*/
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struct gpio_regs {
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volatile uint32_t GPIOFS; /*Function Selection Register */
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volatile uint32_t Reserved1[3];
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volatile uint32_t GPIOOE; /*Output Enable Register */
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volatile uint32_t Reserved2[3];
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volatile uint32_t GPIOD; /*Output Data Register */
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volatile uint32_t Reserved3[3];
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volatile uint32_t GPIOIN; /*Input Data Register */
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volatile uint32_t Reserved4[3];
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volatile uint32_t GPIOPU; /*Pull Up Register */
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volatile uint32_t Reserved5[3];
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volatile uint32_t GPIOOD; /*Open Drain Register */
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volatile uint32_t Reserved6[3];
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volatile uint32_t GPIOIE; /*Input Enable Register */
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volatile uint32_t Reserved7[3];
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volatile uint32_t GPIODC; /*Driving Control Register */
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volatile uint32_t Reserved8[3];
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volatile uint32_t GPIOLV; /*Low Voltage Mode Enable Register */
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volatile uint32_t Reserved9[3];
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volatile uint32_t GPIOPD; /*Pull Down Register */
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volatile uint32_t Reserved10[3];
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volatile uint32_t GPIOFL; /*Function Lock Register */
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volatile uint32_t Reserved11[3];
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};
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#define NUM_KB1200_GPIO_PORTS 4
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/*-- Constant Define --------------------------------------------*/
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#define GPIO00_PWMLED0_PWM8 0x00
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#define GPIO01_SERRXD1_UARTSIN 0x01
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#define GPIO03_SERTXD1_UARTSOUT 0x03
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#define GPIO22_ESBDAT_PWM9 0x22
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#define GPIO28_32KOUT_SERCLK2 0x28
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#define GPIO36_UARTSOUT_SERTXD2 0x36
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#define GPIO5C_KSO6_P80DAT 0x5C
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#define GPIO5D_KSO7_P80CLK 0x5D
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#define GPIO5E_KSO8_SERRXD1 0x5E
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#define GPIO5F_KSO9_SERTXD1 0x5F
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#define GPIO71_SDA8_UARTRTS 0x71
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#define GPIO38_SCL4_PWM1 0x38
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#endif /* ENE_KB1200_GPIO_H */

‎soc/ene/kb1200/reg/gptd.h

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/*
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* Copyright (c) 2023 ENE Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ENE_KB1200_GPTD_H
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#define ENE_KB1200_GPTD_H
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/**
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* Structure type to access GPIO Trigger Detector (GPTD).
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*/
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struct gptd_regs {
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volatile uint32_t GPTDIE; /*Interrupt Enable Register */
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volatile uint32_t Reserved1[3];
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volatile uint32_t GPTDPF; /*Event Pending Flag Register */
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volatile uint32_t Reserved2[3];
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volatile uint32_t GPTDCHG; /*Change Trigger Register */
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volatile uint32_t Reserved3[3];
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volatile uint32_t GPTDEL; /*Level/Edge Trigger Register */
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volatile uint32_t Reserved4[3];
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volatile uint32_t GPTDPS; /*Polarity Selection Register */
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volatile uint32_t Reserved5[3];
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volatile uint32_t GPTDWE; /*WakeUP Enable Register */
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volatile uint32_t Reserved6[3];
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};
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#endif /* ENE_KB1200_GPTD_H */

‎soc/ene/kb1200/reg/pmu.h

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/*
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* Copyright (c) 2023 ENE Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ENE_KB1200_PMU_H
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#define ENE_KB1200_PMU_H
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/**
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* Structure type to access Power Management Unit (PMU).
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*/
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struct pmu_regs {
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volatile uint8_t PMUIDLE; /*IDLE wakeup by Interrupt Register */
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volatile uint8_t Reserved0[3]; /*Reserved */
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volatile uint32_t PMUSTOP; /*STOP Wakeup Source Register */
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volatile uint8_t PMUSTOPC; /*STOP Control Register */
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volatile uint8_t Reserved1[3]; /*Reserved */
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volatile uint8_t PMUCTRL; /*Control Register */
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volatile uint8_t Reserved2[3]; /*Reserved */
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volatile uint8_t PMUSTAF; /*Status Flag */
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volatile uint8_t Reserved3[3]; /*Reserved */
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};
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/* STOP Wakeup Source */
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#define PMU_STOP_WU_GPTD 0x00000001
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#define PMU_STOP_WU_VC0 0x00000002
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#define PMU_STOP_WU_VC1 0x00000004
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#define PMU_STOP_WU_IKB 0x00000010
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#define PMU_STOP_WU_WDT 0x00000100
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#define PMU_STOP_WU_HIBTMR 0x00000400
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#define PMU_STOP_WU_eSPI 0x00010000
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#define PMU_STOP_WU_SPIS 0x00010000
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#define PMU_STOP_WU_I2CD32 0x00020000
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#define PMU_STOP_WU_EDI32 0x00040000
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#define PMU_STOP_WU_SWD 0x00080000
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#define PMU_STOP_WU_ITIM 0x00100000
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#define PMU_STOP_WU_I2CS0 0x01000000
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#define PMU_STOP_WU_I2CS1 0x02000000
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#define PMU_STOP_WU_I2CS2 0x04000000
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#define PMU_STOP_WU_I2CS3 0x08000000
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#define PMU_IDLE_WU_ENABLE 0x00000001
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#endif /* ENE_KB1200_PMU_H */

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