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Tavish Naruka
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drivers: gpio: add TMS570 gpio driver
Adds TI TMS570 SoC GPIO driver. Signed-off-by: Tavish Naruka <[email protected]>
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‎drivers/gpio/CMakeLists.txt‎

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@@ -110,6 +110,7 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_TCA6424A gpio_tca6424a.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_TELINK_B91 gpio_b91.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_TEST gpio_test.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_TLE9104 gpio_tle9104.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_TMS570 gpio_tms570.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_WCH_GPIO wch_gpio_ch32v00x.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_XEC gpio_mchp_xec.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_XEC_V2 gpio_mchp_xec_v2.c)

‎drivers/gpio/Kconfig‎

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@@ -192,6 +192,7 @@ source "drivers/gpio/Kconfig.sy1xx"
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source "drivers/gpio/Kconfig.tca6424a"
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source "drivers/gpio/Kconfig.test"
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source "drivers/gpio/Kconfig.tle9104"
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source "drivers/gpio/Kconfig.tms570"
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source "drivers/gpio/Kconfig.wch_ch32v00x"
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source "drivers/gpio/Kconfig.xec"
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source "drivers/gpio/Kconfig.xlnx"

‎drivers/gpio/Kconfig.tms570‎

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# Copyright (c) 2025 ispace, inc.
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# SPDX-License-Identifier: Apache-2.0
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config GPIO_TMS570
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bool "TMS570 GPIO driver"
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default y
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depends on DT_HAS_TI_TMS570_GPIO_ENABLED
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help
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Enable driver for the TI TMS570 GPIO controller.

‎drivers/gpio/gpio_tms570.c‎

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/*
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* Copyright (c) 2025 ispace, inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ti_tms570_gpio
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/kernel.h>
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#include <zephyr/sys/sys_io.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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#include <zephyr/irq.h>
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/* port registers */
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#define REG_DIR 0x0000 /* Data Direction Register */
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#define REG_DIN 0x0004 /* Data Input Register */
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#define REG_DOUT 0x0008 /* Data Output Register */
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#define REG_DSET 0x000C /* Data Output Set Register */
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#define REG_DCLR 0x0010 /* Data Output Clear Register */
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#define REG_PDR 0x0014 /* Open Drain Register */
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#define REG_PULDIS 0x0018 /* Pullup Disable Register */
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#define REG_PSL 0x001C /* Pull Up/Down Selection Register */
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/* GIO base registers */
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#define REG_GCR0 0x0000 /* Global Control Register */
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#define REG_INTDET 0x0008 /* Interrupt Detect Register*/
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#define REG_POL 0x000C /* Interrupt Polarity Register */
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#define REG_ENASET 0x0010 /* Interrupt Enable Set Register */
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#define REG_ENACLR 0x0014 /* Interrupt Enable Clear Register */
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#define REG_LVLSET 0x0018 /* Interrupt Priority Set Register */
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#define REG_LVLCLR 0x001C /* Interrupt Priority Clear Register */
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#define REG_FLG 0x0020 /* Interrupt Flag Register */
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#define REG_OFF1 0x0024 /* Interrupt Offset A Register */
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#define REG_OFF2 0x0028 /* Interrupt Offset B Register */
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#define REG_EMU1 0x002C /* Emulation 1 Register */
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#define REG_EMU2 0x0030 /* Emulation 2 Register */
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struct gpio_tms570_config {
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/* gpio_driver_config needs to be first */
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struct gpio_driver_config common;
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uint32_t reg_gio;
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uint32_t reg_port;
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};
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struct gpio_tms570_data {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_data common;
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};
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static int gpio_tms570_set_bits(const struct device *dev, gpio_port_pins_t pin)
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{
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const struct gpio_tms570_config *config = dev->config;
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sys_write32(pin, config->reg_port + REG_DOUT);
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return 0;
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}
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static int gpio_tms570_clear_bits(const struct device *dev, gpio_port_pins_t pin)
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{
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const struct gpio_tms570_config *config = dev->config;
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uint32_t val;
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val = sys_read32(config->reg_port + REG_DIN);
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sys_write32(val & (uint32_t)~pin, config->reg_port + REG_DOUT);
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return 0;
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}
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static int gpio_tms570_port_set_masked_raw(const struct device *dev,
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gpio_port_pins_t mask,
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gpio_port_value_t value)
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{
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const struct gpio_tms570_config *config = dev->config;
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uint32_t cur_out;
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uint32_t cur_dir;
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uint32_t val_set;
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uint32_t val_clr;
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cur_out = sys_read32(config->reg_port + REG_DIN);
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cur_dir = sys_read32(config->reg_port + REG_DIR);
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val_clr = cur_dir & cur_out & ~value & mask;
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val_set = cur_dir & ~cur_out & value & mask;
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sys_write32(cur_out & (uint32_t)~val_clr, config->reg_port + REG_DOUT);
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sys_write32(val_set, config->reg_port + REG_DOUT);
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return 0;
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}
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static int gpio_tms570_port_toggle_bits(const struct device *dev,
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gpio_port_pins_t pins)
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{
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const struct gpio_tms570_config *config = dev->config;
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uint32_t cur_out;
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uint32_t cur_dir;
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uint32_t val_set;
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uint32_t val_clr;
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cur_out = sys_read32(config->reg_port + REG_DIN);
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cur_dir = sys_read32(config->reg_port + REG_DIR);
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val_clr = cur_dir & cur_out & pins;
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val_set = cur_dir & ~cur_out & pins;
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sys_write32(cur_out & (uint32_t)~val_clr, config->reg_port + REG_DOUT);
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sys_write32(val_set, config->reg_port + REG_DOUT);
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return 0;
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}
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static int gpio_tms570_get(const struct device *dev, gpio_port_value_t *value)
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{
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const struct gpio_tms570_config *config = dev->config;
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*value = sys_read32(config->reg_port + REG_DIN);
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return 0;
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}
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static int gpio_tms570_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
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{
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const struct gpio_tms570_config *config = dev->config;
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uint32_t current_config;
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int ret;
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/* Read the current configuration of the pins */
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current_config = sys_read32(config->reg_port + REG_DIR);
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/* We only support changes in the direction of the pins */
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if ((flags & GPIO_INPUT) != 0U) {
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/* Pins specified as input will have their DIR register's bit set to 0 */
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sys_write32(current_config & ~BIT(pin), config->reg_port + REG_DIR);
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} else if ((flags & GPIO_OUTPUT) != 0U) {
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/* Pins specified as output will have their DIR register's bit set to 1 */
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sys_write32(current_config | BIT(pin), config->reg_port + REG_DIR);
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if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) {
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ret = gpio_tms570_set_bits(dev, (gpio_port_pins_t)BIT(pin));
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if (ret < 0) {
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return ret;
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}
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} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0U) {
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ret = gpio_tms570_set_bits(dev, (gpio_port_pins_t)BIT(pin));
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if (ret < 0) {
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return ret;
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}
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}
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} else {
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return -EINVAL;
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}
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return 0;
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}
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static int gpio_tms570_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
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enum gpio_int_mode mode, enum gpio_int_trig trig)
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{
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return -ENOTSUP;
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}
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static int gpio_tms570_manage_callback(const struct device *dev, struct gpio_callback *callback,
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bool set)
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{
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return -ENOTSUP;
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}
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static const struct gpio_driver_api gpio_tms570_api = {
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.port_get_raw = gpio_tms570_get,
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.port_set_masked_raw = gpio_tms570_port_set_masked_raw,
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.port_set_bits_raw = gpio_tms570_set_bits,
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.port_clear_bits_raw = gpio_tms570_clear_bits,
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.pin_configure = gpio_tms570_configure,
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.port_toggle_bits = gpio_tms570_port_toggle_bits,
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.pin_interrupt_configure = gpio_tms570_pin_interrupt_configure,
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.manage_callback = gpio_tms570_manage_callback,
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};
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static int gpio_tms570_init(const struct device *dev)
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{
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const struct gpio_tms570_config *config = dev->config;
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static int gpio_tms570_init_done;
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if (gpio_tms570_init_done == 0) {
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gpio_tms570_init_done = 1;
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sys_write32(1, config->reg_gio + REG_GCR0);
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sys_write32(0xFFU, config->reg_gio + REG_ENACLR);
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sys_write32(0xFFU, config->reg_gio + REG_LVLCLR);
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}
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return 0;
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}
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#define TMS570_GPIO_INIT(n) \
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static struct gpio_tms570_data gpio_tms570_data_##n = { \
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}; \
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static struct gpio_tms570_config gpio_tms570_config_##n = { \
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.common = { \
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
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}, \
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.reg_port = DT_INST_REG_ADDR_BY_IDX(n, 0), \
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.reg_gio = DT_INST_REG_ADDR_BY_IDX(n, 1), \
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}; \
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DEVICE_DT_INST_DEFINE(n, gpio_tms570_init, NULL, \
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&gpio_tms570_data_##n, &gpio_tms570_config_##n, \
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POST_KERNEL, CONFIG_GPIO_INIT_PRIORITY, \
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&gpio_tms570_api);
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DT_INST_FOREACH_STATUS_OKAY(TMS570_GPIO_INIT)

‎dts/arm/ti/tms570.dtsi‎

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reg = <0xfff7e500 256>;
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status = "disabled";
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};
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gpio_a: gpio@fff7bc34 {
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compatible = "ti,tms570-gpio";
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reg = <0xfff7bc34 0x34 /* GIO port base */
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0xfff7bc00 0x20>; /* GIO base */
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interrupts = <13 0>;
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interrupt-parent = <&vim>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <8>;
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status = "okay";
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};
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gpio_b: gpio@fff7bc54 {
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compatible = "ti,tms570-gpio";
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reg = <0xfff7bc54 0x34 /* GIO port base */
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0xfff7bc00 0x20>; /* GIO base */
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interrupts = <13 0>;
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interrupt-parent = <&vim>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <8>;
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status = "okay";
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};
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};
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};

‎dts/bindings/gpio/ti,tms570-gpio.yaml‎

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# Copyright (c) 2025 ispace, inc.
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# SPDX-License-Identifier: Apache-2.0
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description: TMS570 GPIO
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compatible: "ti,tms570-gpio"
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include: [gpio-controller.yaml, base.yaml]
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properties:
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# NOTE: Register ranges:
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# - 0 : GIO port registers
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# - 1 : GIO base registers
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reg:
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required: true
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interrupt-parent:
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required: true
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ngpios:
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required: true
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gpio-cells:
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- pin
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- flags

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