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peterwangsz
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boards: frdm_mcxa166, frdm_mcxa276: add uart support
1. add uart support 2. enable the uart_async_api test example Signed-off-by: Peter Wang <[email protected]>
1 parent b983b04 commit 393c8d1

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10 files changed

+216
-6
lines changed

10 files changed

+216
-6
lines changed

‎boards/nxp/frdm_mcxa166/board.c‎

Lines changed: 18 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -123,21 +123,36 @@ void board_early_init_hook(void)
123123
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart0))
124124
CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
125125
CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART0);
126-
RESET_PeripheralReset(kLPUART0_RST_SHIFT_RSTn);
126+
RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn);
127127
#endif
128128

129129
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart1))
130130
CLOCK_SetClockDiv(kCLOCK_DivLPUART1, 1u);
131131
CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART1);
132-
RESET_PeripheralReset(kLPUART1_RST_SHIFT_RSTn);
132+
RESET_ReleasePeripheralReset(kLPUART1_RST_SHIFT_RSTn);
133133
#endif
134134

135135
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart2))
136136
CLOCK_SetClockDiv(kCLOCK_DivLPUART2, 1u);
137137
CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART2);
138-
RESET_PeripheralReset(kLPUART2_RST_SHIFT_RSTn);
138+
RESET_ReleasePeripheralReset(kLPUART2_RST_SHIFT_RSTn);
139139
#endif
140140

141+
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart3))
142+
CLOCK_SetClockDiv(kCLOCK_DivLPUART3, 1u);
143+
CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART3);
144+
RESET_ReleasePeripheralReset(kLPUART3_RST_SHIFT_RSTn);
145+
#endif
146+
147+
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart4))
148+
CLOCK_SetClockDiv(kCLOCK_DivLPUART4, 1u);
149+
CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART4);
150+
RESET_ReleasePeripheralReset(kLPUART4_RST_SHIFT_RSTn);
151+
#endif
152+
153+
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(edma0))
154+
RESET_ReleasePeripheralReset(kDMA0_RST_SHIFT_RSTn);
155+
#endif
141156
/* Set SystemCoreClock variable. */
142157
SystemCoreClock = CLOCK_INIT_CORE_CLOCK;
143158
}

‎boards/nxp/frdm_mcxa166/frdm_mcxa166-pinctrl.dtsi‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,4 +17,13 @@
1717
};
1818
};
1919

20+
pinmux_lpuart3: pinmux_lpuart3 {
21+
group0 {
22+
pinmux = <LPUART3_RXD_P4_2>,
23+
<LPUART3_TXD_P4_5>;
24+
drive-strength = "low";
25+
slew-rate = "fast";
26+
input-enable;
27+
};
28+
};
2029
};

‎boards/nxp/frdm_mcxa166/frdm_mcxa166.yaml‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,4 +15,5 @@ toolchain:
1515
- gnuarmemb
1616
supported:
1717
- gpio
18+
- uart
1819
vendor: nxp

‎boards/nxp/frdm_mcxa276/board.c‎

Lines changed: 18 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -123,21 +123,36 @@ void board_early_init_hook(void)
123123
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart0))
124124
CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
125125
CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART0);
126-
RESET_PeripheralReset(kLPUART0_RST_SHIFT_RSTn);
126+
RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn);
127127
#endif
128128

129129
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart1))
130130
CLOCK_SetClockDiv(kCLOCK_DivLPUART1, 1u);
131131
CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART1);
132-
RESET_PeripheralReset(kLPUART1_RST_SHIFT_RSTn);
132+
RESET_ReleasePeripheralReset(kLPUART1_RST_SHIFT_RSTn);
133133
#endif
134134

135135
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart2))
136136
CLOCK_SetClockDiv(kCLOCK_DivLPUART2, 1u);
137137
CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART2);
138-
RESET_PeripheralReset(kLPUART2_RST_SHIFT_RSTn);
138+
RESET_ReleasePeripheralReset(kLPUART2_RST_SHIFT_RSTn);
139139
#endif
140140

141+
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart3))
142+
CLOCK_SetClockDiv(kCLOCK_DivLPUART3, 1u);
143+
CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART3);
144+
RESET_ReleasePeripheralReset(kLPUART3_RST_SHIFT_RSTn);
145+
#endif
146+
147+
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart4))
148+
CLOCK_SetClockDiv(kCLOCK_DivLPUART4, 1u);
149+
CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART4);
150+
RESET_ReleasePeripheralReset(kLPUART4_RST_SHIFT_RSTn);
151+
#endif
152+
153+
#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(edma0))
154+
RESET_ReleasePeripheralReset(kDMA0_RST_SHIFT_RSTn);
155+
#endif
141156
/* Set SystemCoreClock variable. */
142157
SystemCoreClock = CLOCK_INIT_CORE_CLOCK;
143158
}

‎boards/nxp/frdm_mcxa276/frdm_mcxa276-pinctrl.dtsi‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,4 +17,13 @@
1717
};
1818
};
1919

20+
pinmux_lpuart3: pinmux_lpuart3 {
21+
group0 {
22+
pinmux = <LPUART3_RXD_P4_2>,
23+
<LPUART3_TXD_P4_5>;
24+
drive-strength = "low";
25+
slew-rate = "fast";
26+
input-enable;
27+
};
28+
};
2029
};

‎boards/nxp/frdm_mcxa276/frdm_mcxa276.yaml‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,4 +15,5 @@ toolchain:
1515
- gnuarmemb
1616
supported:
1717
- gpio
18+
- uart
1819
vendor: nxp

‎dts/arm/nxp/nxp_mcxa166.dtsi‎

Lines changed: 61 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -130,12 +130,59 @@
130130
nxp,kinetis-port = <&porte>;
131131
};
132132

133+
lpuart0: lpuart@4009f000 {
134+
compatible = "nxp,lpuart";
135+
status = "disabled";
136+
reg = <0x4009f000 0x1000>;
137+
interrupts = <31 0>;
138+
clocks = <&syscon MCUX_LPUART0_CLK>;
139+
/* DMA channels 0 and 1 muxed to LPUART0 RX and TX */
140+
dmas = <&edma0 0 21>, <&edma0 1 22>;
141+
dma-names = "rx", "tx";
142+
};
143+
144+
lpuart1: lpuart@4009a000 {
145+
compatible = "nxp,lpuart";
146+
status = "disabled";
147+
reg = <0x4009a000 0x1000>;
148+
interrupts = <32 0>;
149+
clocks = <&syscon MCUX_LPUART1_CLK>;
150+
/* DMA channels 2 and 3 muxed to LPUART1 RX and TX */
151+
dmas = <&edma0 2 23>, <&edma0 3 24>;
152+
dma-names = "rx", "tx";
153+
};
154+
133155
lpuart2: lpuart@400a1000 {
134156
compatible = "nxp,lpuart";
135157
status = "disabled";
136158
reg = <0x400a1000 0x1000>;
137159
interrupts = <33 0>;
138160
clocks = <&syscon MCUX_LPUART2_CLK>;
161+
/* DMA channels 4 and 5, muxed to LPUART2 RX and TX */
162+
dmas = <&edma0 4 25>, <&edma0 5 26>;
163+
dma-names = "rx", "tx";
164+
};
165+
166+
lpuart3: lpuart@400a2000 {
167+
compatible = "nxp,lpuart";
168+
status = "disabled";
169+
reg = <0x400a2000 0x1000>;
170+
interrupts = <34 0>;
171+
clocks = <&syscon MCUX_LPUART3_CLK>;
172+
/* DMA channels 2 and 3, muxed to LPUART3 RX and TX */
173+
dmas = <&edma0 6 27>, <&edma0 7 28>;
174+
dma-names = "rx", "tx";
175+
};
176+
177+
lpuart4: lpuart@400a3000 {
178+
compatible = "nxp,lpuart";
179+
status = "disabled";
180+
reg = <0x400a3000 0x1000>;
181+
interrupts = <34 0>;
182+
clocks = <&syscon MCUX_LPUART4_CLK>;
183+
/* DMA channels 0 and 1 muxed to LPUART4 RX and TX */
184+
dmas = <&edma0 0 29>, <&edma0 1 30>;
185+
dma-names = "rx", "tx";
139186
};
140187

141188
fmu: flash-controller@40095000 {
@@ -153,6 +200,20 @@
153200
write-block-size = <128>;
154201
};
155202
};
203+
204+
edma0: dma-controller@40080000 {
205+
#dma-cells = <2>;
206+
compatible = "nxp,mcux-edma";
207+
nxp,version = <4>;
208+
dma-channels = <8>;
209+
dma-requests = <131>;
210+
211+
reg = <0x40080000 0x1000>;
212+
interrupts = <2 0>, <3 0>, <4 0>, <5 0>,
213+
<6 0>, <7 0>, <8 0>, <9 0>;
214+
no-error-irq;
215+
status = "disabled";
216+
};
156217
};
157218
};
158219

‎dts/arm/nxp/nxp_mcxa276.dtsi‎

Lines changed: 61 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -130,12 +130,59 @@
130130
nxp,kinetis-port = <&porte>;
131131
};
132132

133+
lpuart0: lpuart@4009f000 {
134+
compatible = "nxp,lpuart";
135+
status = "disabled";
136+
reg = <0x4009f000 0x1000>;
137+
interrupts = <31 0>;
138+
clocks = <&syscon MCUX_LPUART0_CLK>;
139+
/* DMA channels 0 and 1 muxed to LPUART0 RX and TX */
140+
dmas = <&edma0 0 21>, <&edma0 1 22>;
141+
dma-names = "rx", "tx";
142+
};
143+
144+
lpuart1: lpuart@4009a000 {
145+
compatible = "nxp,lpuart";
146+
status = "disabled";
147+
reg = <0x4009a000 0x1000>;
148+
interrupts = <32 0>;
149+
clocks = <&syscon MCUX_LPUART1_CLK>;
150+
/* DMA channels 2 and 3 muxed to LPUART1 RX and TX */
151+
dmas = <&edma0 2 23>, <&edma0 3 24>;
152+
dma-names = "rx", "tx";
153+
};
154+
133155
lpuart2: lpuart@400a1000 {
134156
compatible = "nxp,lpuart";
135157
status = "disabled";
136158
reg = <0x400a1000 0x1000>;
137159
interrupts = <33 0>;
138160
clocks = <&syscon MCUX_LPUART2_CLK>;
161+
/* DMA channels 4 and 5, muxed to LPUART2 RX and TX */
162+
dmas = <&edma0 4 25>, <&edma0 5 26>;
163+
dma-names = "rx", "tx";
164+
};
165+
166+
lpuart3: lpuart@400a2000 {
167+
compatible = "nxp,lpuart";
168+
status = "disabled";
169+
reg = <0x400a2000 0x1000>;
170+
interrupts = <34 0>;
171+
clocks = <&syscon MCUX_LPUART3_CLK>;
172+
/* DMA channels 2 and 3, muxed to LPUART3 RX and TX */
173+
dmas = <&edma0 6 27>, <&edma0 7 28>;
174+
dma-names = "rx", "tx";
175+
};
176+
177+
lpuart4: lpuart@400a3000 {
178+
compatible = "nxp,lpuart";
179+
status = "disabled";
180+
reg = <0x400a3000 0x1000>;
181+
interrupts = <34 0>;
182+
clocks = <&syscon MCUX_LPUART4_CLK>;
183+
/* DMA channels 0 and 1 muxed to LPUART4 RX and TX */
184+
dmas = <&edma0 0 29>, <&edma0 1 30>;
185+
dma-names = "rx", "tx";
139186
};
140187

141188
fmu: flash-controller@40095000 {
@@ -153,6 +200,20 @@
153200
write-block-size = <128>;
154201
};
155202
};
203+
204+
edma0: dma-controller@40080000 {
205+
#dma-cells = <2>;
206+
compatible = "nxp,mcux-edma";
207+
nxp,version = <4>;
208+
dma-channels = <8>;
209+
dma-requests = <131>;
210+
211+
reg = <0x40080000 0x1000>;
212+
interrupts = <2 0>, <3 0>, <4 0>, <5 0>,
213+
<6 0>, <7 0>, <8 0>, <9 0>;
214+
no-error-irq;
215+
status = "disabled";
216+
};
156217
};
157218
};
158219

‎tests/drivers/uart/uart_async_api/boards/frdm_mcxa166.overlay‎

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
1+
/*
2+
* Copyright 2025 NXP
3+
* SPDX-License-Identifier: Apache-2.0
4+
*/
5+
6+
/*
7+
* Short J5.3 and J5.4 to loopback LPUART3 RX/TX for this test
8+
* or test lpuart3 with "nxp,loopback"
9+
*/
10+
dut: &lpuart3 {
11+
status = "okay";
12+
current-speed = <115200>;
13+
pinctrl-0 = <&pinmux_lpuart3>;
14+
pinctrl-names = "default";
15+
};
16+
17+
&edma0 {
18+
status = "okay";
19+
};

‎tests/drivers/uart/uart_async_api/boards/frdm_mcxa276.overlay‎

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
1+
/*
2+
* Copyright 2025 NXP
3+
* SPDX-License-Identifier: Apache-2.0
4+
*/
5+
6+
/*
7+
* Short J5.3 and J5.4 to loopback LPUART3 RX/TX for this test
8+
* or test lpuart3 with "nxp,loopback"
9+
*/
10+
dut: &lpuart3 {
11+
status = "okay";
12+
current-speed = <115200>;
13+
pinctrl-0 = <&pinmux_lpuart3>;
14+
pinctrl-names = "default";
15+
};
16+
17+
&edma0 {
18+
status = "okay";
19+
};

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