soc: arm: stm32f7 soc without Dcache

The stm32f7 (like stm32H7) should be able to disable
the Dcache when using the DMA. This is to avoid any
pb of cache coherency on the DMA buffers.

Signed-off-by: Francois Ramu <[email protected]>

Author: FRASTM

soc/arm/st_stm32/stm32f7/soc.c

@@ -37,8 +37,11 @@ static int st_stm32f7_init(const struct device *arg)
 	key = irq_lock();
 
 	SCB_EnableICache();
-	if (!(SCB->CCR & SCB_CCR_DC_Msk)) {
-		SCB_EnableDCache();
+
+	if (IS_ENABLED(CONFIG_DCACHE)) {
+		if (!(SCB->CCR & SCB_CCR_DC_Msk)) {
+			SCB_EnableDCache();
+		}
 	}
 
 	/* Install default handler that simply resets the CPU