dts: bindings: gpio: add sifli,sf32lb-gpio-parent

SiFli SF32LB SoCs have a single GPIO controller block which manages all
pins (> 32). However, Zephyr API expects ports to have up to 32 pins. So
in order to make things compatible, we introduce a Zephyrism in
devicetree: a parent node with common properties (e.g. IRQ, RCC clock,
etc.) and children nodes for each 32 pin block. See upcoming devicetree
definition for more details.

Signed-off-by: Gerard Marull-Paretas <[email protected]>

Author: gmarull

dts/bindings/gpio/sifli,sf32lb-gpio-parent.yaml

@@ -0,0 +1,28 @@
+# Copyright (c) 2025 Core Devices LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: SF32LB GPIO (parent)
+
+compatible: "sifli,sf32lb-gpio-parent"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
+
+  ranges:
+    type: array
+    required: true
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 1
+
+  clocks:
+    required: true
+
+  interrupts:
+    required: true