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board: pinctrl: board config for RT1060
enable pin control for RT1060 EVK. Signed-off-by: Hake Huang <[email protected]> Signed-off-by: Daniel DeGrasse <[email protected]>
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4 files changed

+64
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@@ -0,0 +1,53 @@
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/*
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* Copyright (c) 2022, NXP
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* SPDX-License-Identifier: Apache-2.0
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*
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* Generated by rt_cfg_utils.py on 2022-03-02
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*/
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#include <nxp/nxp_imx/rt/mimxrt1062-iomuxc.dtsi>
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&pinctrl {
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lpuart1_default: lpuart1_default {
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group0 {
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pinmux = <&iomuxc_gpio_ad_b0_12_lpuart1_tx
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&iomuxc_gpio_ad_b0_13_lpuart1_rx>;
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drive-strength = "r0-6";
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slew-rate = "slow";
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nxp,speed = "100-mhz";
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};
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};
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lpuart1_sleep: pinmux_lpuart1_sleep {
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group0 {
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pinmux = <&iomuxc_gpio_ad_b0_13_gpio1_io13>;
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bias-disable;
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drive-strength = "r0";
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bias-pull-up;
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bias-pull-up-value = "100k";
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slew-rate = "slow";
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nxp,speed = "50-mhz";
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};
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group1 {
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pinmux = <&iomuxc_gpio_ad_b0_12_lpuart1_tx>;
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drive-strength = "r0-6";
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slew-rate = "slow";
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nxp,speed = "100-mhz";
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};
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};
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sai1_default: sai1_default {
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group0 {
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pinmux = <&iomuxc_gpio_ad_b1_09_sai1_mclk
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&iomuxc_gpio_ad_b1_13_sai1_tx_data00
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&iomuxc_gpio_ad_b1_12_sai1_rx_data00
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&iomuxc_gpio_ad_b1_14_sai1_tx_bclk
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&iomuxc_gpio_ad_b1_15_sai1_tx_sync>;
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drive-strength = "r0-6";
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slew-rate = "slow";
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nxp,speed = "100-mhz";
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input-enable;
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};
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};
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};

boards/arm/mimxrt1060_evk/mimxrt1060_evk.dts

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@@ -7,6 +7,7 @@
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/dts-v1/;
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#include <nxp/nxp_rt1060.dtsi>
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#include "mimxrt1060_evk-pinctrl.dtsi"
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/ {
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model = "NXP MIMXRT1060-EVK board";
@@ -175,6 +176,9 @@ arduino_serial: &lpuart3 {};
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&lpuart1 {
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status = "okay";
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current-speed = <115200>;
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pinctrl-0 = <&lpuart1_default>;
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pinctrl-1 = <&lpuart1_sleep>;
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pinctrl-names = "default", "sleep";
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};
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&enet {
@@ -229,6 +233,8 @@ zephyr_udc0: &usb1 {
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&sai1 {
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status = "okay";
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pinctrl-0 = <&sai1_default>;
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pinctrl-names = "default";
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};
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/* Enable GPT for use as a hardware timer. This disables Cortex Systick.
@@ -237,3 +243,7 @@ zephyr_udc0: &usb1 {
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&gpt_hw_timer {
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status = "okay";
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};
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&iomuxcgpr {
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status = "okay";
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};

boards/arm/mimxrt1060_evk/mimxrt1060_evk_defconfig

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@@ -13,3 +13,4 @@ CONFIG_SERIAL=y
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CONFIG_GPIO=y
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CONFIG_ARM_MPU=y
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CONFIG_HW_STACK_PROTECTION=y
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CONFIG_PINCTRL=y

boards/arm/mimxrt1060_evk/pinmux.c

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@@ -114,22 +114,6 @@ static int mimxrt1060_evk_init(const struct device *dev)
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IOMUXC_SetPinMux(IOMUXC_SNVS_WAKEUP_GPIO5_IO00, 0);
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart1), okay) && CONFIG_SERIAL
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/* LPUART1 TX/RX */
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_LPUART1_TX, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_LPUART1_TX,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart3), okay) && CONFIG_SERIAL
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/* LPUART3 TX/RX */
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_LPUART3_TX, 0);
@@ -400,20 +384,6 @@ static int mimxrt1060_evk_init(const struct device *dev)
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IOMUXC_SW_PAD_CTL_PAD_DSE(6));
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(sai1), okay) && CONFIG_I2S
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_09_SAI1_MCLK, 1U);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00, 1U);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00, 1U);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK, 1U);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC, 1U);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_09_SAI1_MCLK, 0x10B0u);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00, 0x10B0u);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00, 0x10B0u);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK, 0x10B0u);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC, 0x10B0u);
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#endif
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return 0;
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}
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