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boards: shields: add support for rtkmipilcdb00000be shield
First commit to support rtkmipilcdb00000be display shield Signed-off-by: The Nguyen <[email protected]>
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‎boards/renesas/ek_ra8d1/Kconfig.defconfig

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@@ -10,4 +10,18 @@ config NET_L2_ETHERNET
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1111
endif # NETWORKING
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if SHIELD_RTKMIPILCDB00000BE
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config MEMC
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default y
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if LVGL
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config LV_Z_VBD_CUSTOM_SECTION
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default y
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endif # LVGL
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endif # SHIELD_RTKMIPILCDB00000BE
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endif # BOARD_EK_RA8D1

‎boards/renesas/ek_ra8d1/doc/index.rst

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@@ -85,39 +85,42 @@ Supported Features
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The below features are currently supported on Zephyr OS for EK-RA8D1 board:
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+--------------+------------+------------------+
89-
| Interface | Controller | Driver/Component |
90-
+==============+============+==================+
91-
| GPIO | on-chip | gpio |
92-
+--------------+------------+------------------+
93-
| MPU | on-chip | arch/arm |
94-
+--------------+------------+------------------+
95-
| NVIC | on-chip | arch/arm |
96-
+--------------+------------+------------------+
97-
| UART | on-chip | serial |
98-
+--------------+------------+------------------+
99-
| CLOCK | on-chip | clock control |
100-
+--------------+------------+------------------+
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| ENTROPY | on-chip | entropy |
102-
+--------------+------------+------------------+
103-
| SPI | on-chip | spi |
104-
+--------------+------------+------------------+
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| FLASH | on-chip | flash |
106-
+--------------+------------+------------------+
107-
| PWM | on-chip | pwm |
108-
+--------------+------------+------------------+
109-
| COUNTER | on-chip | counter |
110-
+--------------+------------+------------------+
111-
| CAN | on-chip | canfd |
112-
+--------------+------------+------------------+
113-
| I2C | on-chip | i2c |
114-
+--------------+------------+------------------+
115-
| USBHS | on-chip | udc |
116-
+--------------+------------+------------------+
117-
| ETHERNET | on-chip | ethernet |
118-
+--------------+------------+------------------+
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| ADC | on-chip | adc |
120-
+--------------+------------+------------------+
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+--------------+------------+-----------------------------------+
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| Interface | Controller | Driver/Component |
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+==============+============+===================================+
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| GPIO | on-chip | gpio |
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+--------------+------------+-----------------------------------+
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| MPU | on-chip | arch/arm |
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+--------------+------------+-----------------------------------+
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| NVIC | on-chip | arch/arm |
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+--------------+------------+-----------------------------------+
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| UART | on-chip | serial |
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+--------------+------------+-----------------------------------+
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| CLOCK | on-chip | clock control |
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+--------------+------------+-----------------------------------+
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| ENTROPY | on-chip | entropy |
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+--------------+------------+-----------------------------------+
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| SPI | on-chip | spi |
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+--------------+------------+-----------------------------------+
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| FLASH | on-chip | flash |
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+--------------+------------+-----------------------------------+
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| PWM | on-chip | pwm |
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+--------------+------------+-----------------------------------+
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| COUNTER | on-chip | counter |
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+--------------+------------+-----------------------------------+
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| CAN | on-chip | canfd |
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+--------------+------------+-----------------------------------+
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| I2C | on-chip | i2c |
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+--------------+------------+-----------------------------------+
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| USBHS | on-chip | udc |
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+--------------+------------+-----------------------------------+
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| DISPLAY | on-chip | LCDIF; MIPI-DSI. Tested with |
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| | | :ref:`rtkmipilcdb00000be` shields |
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+--------------+------------+-----------------------------------+
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| ETHERNET | on-chip | ethernet |
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+--------------+------------+-----------------------------------+
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| ADC | on-chip | adc |
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+--------------+------------+-----------------------------------+
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**Note:** for using Ethernet on RA8D1 board please set switch SW1 as following configuration:
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‎boards/renesas/ek_ra8d1/ek_ra8d1-pinctrl.dtsi

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@@ -178,4 +178,69 @@
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<RA_PSEL(RA_PSEL_BUS, 10, 10)>;
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};
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};
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glcdc_default: glcdc_default {
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group1 {
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/* LCDC_TCON0 */
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psels = <RA_PSEL(RA_PSEL_GLCDC, 8, 5)>,
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/* LCDC_TCON1 */
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<RA_PSEL(RA_PSEL_GLCDC, 8, 7)>,
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/* LCDC_TCON2 */
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<RA_PSEL(RA_PSEL_GLCDC, 5, 13)>,
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/* LCDC_TCON3 */
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<RA_PSEL(RA_PSEL_GLCDC, 5, 15)>,
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/* LCDC_DATA00 */
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<RA_PSEL(RA_PSEL_GLCDC, 9, 14)>,
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/* LCDC_DATA01 */
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<RA_PSEL(RA_PSEL_GLCDC, 9, 15)>,
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/* LCDC_DATA02 */
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<RA_PSEL(RA_PSEL_GLCDC, 9, 10)>,
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/* LCDC_DATA03 */
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<RA_PSEL(RA_PSEL_GLCDC, 9, 11)>,
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/* LCDC_DATA04 */
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<RA_PSEL(RA_PSEL_GLCDC, 9, 12)>,
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/* LCDC_DATA05 */
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<RA_PSEL(RA_PSEL_GLCDC, 9, 13)>,
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/* LCDC_DATA06 */
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<RA_PSEL(RA_PSEL_GLCDC, 9, 4)>,
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/* LCDC_DATA07 */
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<RA_PSEL(RA_PSEL_GLCDC, 9, 3)>,
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/* LCDC_DATA08 */
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<RA_PSEL(RA_PSEL_GLCDC, 9, 2)>,
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/* LCDC_DATA09 */
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<RA_PSEL(RA_PSEL_GLCDC, 2, 7)>,
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/* LCDC_DATA10 */
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<RA_PSEL(RA_PSEL_GLCDC, 7, 11)>,
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/* LCDC_DATA11 */
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<RA_PSEL(RA_PSEL_GLCDC, 7, 12)>,
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/* LCDC_DATA12 */
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<RA_PSEL(RA_PSEL_GLCDC, 7, 13)>,
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/* LCDC_DATA13 */
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<RA_PSEL(RA_PSEL_GLCDC, 7, 14)>,
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/* LCDC_DATA14 */
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<RA_PSEL(RA_PSEL_GLCDC, 7, 15)>,
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/* LCDC_DATA15 */
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<RA_PSEL(RA_PSEL_GLCDC, 11, 7)>,
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/* LCDC_DATA16 */
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<RA_PSEL(RA_PSEL_GLCDC, 11, 6)>,
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/* LCDC_DATA17 */
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<RA_PSEL(RA_PSEL_GLCDC, 11, 5)>,
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/* LCDC_DATA18 */
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<RA_PSEL(RA_PSEL_GLCDC, 11, 1)>,
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/* LCDC_DATA19 */
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<RA_PSEL(RA_PSEL_GLCDC, 11, 4)>,
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/* LCDC_DATA20 */
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<RA_PSEL(RA_PSEL_GLCDC, 11, 3)>,
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/* LCDC_DATA21 */
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<RA_PSEL(RA_PSEL_GLCDC, 11, 2)>,
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/* LCDC_DATA22 */
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<RA_PSEL(RA_PSEL_GLCDC, 11, 0)>,
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/* LCDC_DATA23 */
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<RA_PSEL(RA_PSEL_GLCDC, 7, 7)>,
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/* LCDC_CLK */
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<RA_PSEL(RA_PSEL_GLCDC, 8, 6)>,
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/* LCDC_EXTCLK */
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<RA_PSEL(RA_PSEL_GLCDC, 5, 14)>;
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};
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};
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};

‎boards/renesas/ek_ra8d1/ek_ra8d1.dts

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@@ -65,10 +65,23 @@
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status = "okay";
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};
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renesas_mipi_connector: mipi-connector {
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compatible = "renesas,ra-gpio-mipi-header";
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#gpio-cells = <2>;
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gpio-map-mask = <0xffffffff 0xffffffc0>;
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gpio-map-pass-thru = <0 0x3f>;
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gpio-map = <14 0 &ioport5 11 0>, /* IIC_SDA */
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<15 0 &ioport4 4 0>, /* DISP_BLEN */
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<16 0 &ioport5 12 0>, /* IIC_SCL */
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<17 0 &ioport5 10 0>, /* DISP_INT */
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<18 0 &ioporta 1 0>; /* DISP_RST */
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};
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aliases {
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led0 = &led1;
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sw0 = &button0;
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sw1 = &button1;
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mipi-dsi = &mipi_dsi;
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};
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};
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@@ -111,6 +124,12 @@
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status = "okay";
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};
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&lcdclk {
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clocks = <&pll>;
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div = <2>;
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status = "okay";
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};
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&ioport0 {
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status = "okay";
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};
@@ -123,10 +142,18 @@
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status = "okay";
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};
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&ioport5 {
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status = "okay";
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};
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&ioport6 {
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status = "okay";
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};
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&ioporta {
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status = "okay";
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};
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&sci0 {
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/* sci0 and spi0 cannot be enabled together */
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pinctrl-0 = <&sci9_default>;
@@ -262,3 +289,12 @@
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SDRAM_TREFW_8CYCLES>;
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};
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};
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zephyr_lcdif: &lcdif {
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pinctrl-0 = <&glcdc_default>;
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pinctrl-names = "default";
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};
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zephyr_mipi_dsi: &mipi_dsi {};
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renesas_mipi_i2c: &iic1{};

‎boards/renesas/ek_ra8d1/sdram.ld

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@@ -10,6 +10,9 @@ SECTION_DATA_PROLOGUE(.sdram,(NOLOAD),)
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{
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__SDRAM_Start = .;
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KEEP(*(.sdram*))
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#ifdef CONFIG_LVGL
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KEEP(*(.lvgl_buf*))
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#endif
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__SDRAM_End = .;
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} GROUP_LINK_IN(SDRAM)
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‎boards/shields/rtkmipilcdb00000be/Kconfig.defconfig

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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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if SHIELD_RTKMIPILCDB00000BE
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if DISPLAY
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# Enable MIPI DSI, as this display controller requires it.
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config MIPI_DSI
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default y
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endif # DISPLAY
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if LVGL
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# Configure LVGL to use touchscreen with input API
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config INPUT
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default y
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if INPUT
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# GT911 driver drives reset pin low, GT911 and ILI9806E_DSI driver share a reset line,
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# so it needs to initialize before the display_ili9806e_dsi driver but after the MIPI DSI driver
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config INPUT_INIT_PRIORITY
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default 89
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endif # INPUT
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# LVGL should allocate buffers equal to size of display
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config LV_Z_VDB_SIZE
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default 100
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# Enable double buffering
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config LV_Z_DOUBLE_VDB
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default y
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# Force full refresh. This prevents memory copy associated with partial
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# display refreshes, which is not necessary for the GLCDC driver
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config LV_Z_FULL_REFRESH
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default y
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config LV_Z_BITS_PER_PIXEL
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default 32
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# Use offloaded render thread
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config LV_Z_FLUSH_THREAD
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default y
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choice LV_COLOR_DEPTH
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default LV_COLOR_DEPTH_32
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endchoice
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endif # LVGL
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endif # SHIELD_RTKMIPILCDB00000BE

‎boards/shields/rtkmipilcdb00000be/Kconfig.shield

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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SHIELD_RTKMIPILCDB00000BE
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def_bool $(shields_list_contains,rtkmipilcdb00000be)

‎boards/shields/rtkmipilcdb00000be/boards/ek_ra8d1.overlay

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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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&pinctrl {
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iic1_default: iic1_default {
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group1 {
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/* SCL1 SDA1 */
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psels = <RA_PSEL(RA_PSEL_I2C, 5, 12)>,
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<RA_PSEL(RA_PSEL_I2C, 5, 11)>;
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drive-strength = "medium";
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};
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};
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};
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&iic1 {
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status = "okay";
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <DT_FREQ_K(100)>;
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pinctrl-0 = <&iic1_default>;
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pinctrl-names = "default";
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};

‎boards/shields/rtkmipilcdb00000be/doc/index.rst

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.. _rtkmipilcdb00000be:
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RTKMIPILCDB00000BE MIPI Display
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###############################
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Overview
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********
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The Focus LCDs RTKMIPILCDB00000BE MIPI Display is a 4.5 inch TFT 480x854 pixels
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capacitive touch panel, and a backlight unit.
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This display uses a 26 pin connector header.
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Pins Assignment of the Renesas RTKMIPILCDB00000BE MIPI Display
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==============================================================
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17+
+-----------------------+------------------------+
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| Connector Pin | Function |
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+=======================+========================+
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| 14 | Touch ctrl I2C SDA |
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+-----------------------+------------------------+
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| 15 | Display backlight enable|
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+-----------------------+------------------------+
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| 16 | Touch ctrl I2C SCL |
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+-----------------------+------------------------+
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| 17 | External interrupt |
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+-----------------------+------------------------+
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| 18 | Display reset |
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+-----------------------+------------------------+
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Hardware Requirements:
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**********************
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Supported Renesas RA boards: EK-RA8D1
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- 1 x RA Board
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- 1 x Micro USB cable
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Hardware Configuration:
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***********************
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The MIPI Graphics Expansion Port (J58) connects the EK-RA8D1 board to the MIPI Graphics Expansion Board
42+
supplied as part of the kit.
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Set the configuration switches (SW1) as below to avoid potential failures.
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+-------------+-------------+--------------+------------+------------+------------+-------------+-----------+
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| SW1-1 PMOD1 | SW1-2 TRACE | SW1-3 CAMERA | SW1-4 ETHA | SW1-5 ETHB | SW1-6 GLCD | SW1-7 SDRAM | SW1-8 I3C |
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+-------------+-------------+--------------+------------+------------+------------+-------------+-----------+
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| OFF | OFF | OFF | OFF | OFF | ON | ON | OFF |
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+-------------+-------------+--------------+------------+------------+------------+-------------+-----------+
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Programming
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***********
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Set ``--shield=rtkmipilcdb00000be`` when you invoke ``west build``. For
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example:
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.. zephyr-app-commands::
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:zephyr-app: tests/drivers/display/display_read_write
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:board: ek_ra8d1
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:shield: rtkmipilcdb00000be
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:goals: build

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