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dts: clock: PIC32CM_JH: Add clock control driver bindings
Add bindings for dfll, fdpll, gclk generator, mclk cpu, osc32k, rtc clock and xosc. Signed-off-by: Sunil Abraham <[email protected]>
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‎dts/arm/microchip/pic32c/pic32cm_jh/common/pic32cm_jh.dtsi‎

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#include <arm/armv6-m.dtsi>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/clock/mchp_pic32cm_jh_clock.h>
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/ {
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cpus {
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compatible = "mmio-sram";
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};
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clock: clock@40000800 {
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compatible = "microchip,pic32cm-jh-clock";
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reg = <0x40000800 0x24>, <0x40001000 0x58>,
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<0x40001400 0x20>, <0x40001c00 0x140>;
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reg-names = "mclk", "oscctrl",
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"osc32kctrl", "gclk";
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xosc: xosc {
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compatible = "microchip,pic32cm-jh-xosc";
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};
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osc48m: osc48m {
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compatible = "microchip,pic32cm-jh-osc48m";
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};
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fdpll: fdpll {
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compatible = "microchip,pic32cm-jh-fdpll";
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};
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rtcclock: rtcclock {
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compatible = "microchip,pic32cm-jh-rtc";
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#clock-cells = <1>;
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};
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xosc32k: xosc32k {
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compatible = "microchip,pic32cm-jh-xosc32k";
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};
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osc32k: osc32k {
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compatible = "microchip,pic32cm-jh-osc32k";
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};
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gclkgen: gclkgen {
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compatible = "microchip,pic32cm-jh-gclkgen";
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};
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gclkperiph: gclkperiph {
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compatible = "microchip,pic32cm-jh-gclkperiph";
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#clock-cells = <1>;
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};
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mclkcpu: mclkcpu {
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compatible = "microchip,pic32cm-jh-mclkcpu";
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mclk-cpu-div = <1>;
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};
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mclkperiph: mclkperiph {
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compatible = "microchip,pic32cm-jh-mclkperiph";
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#clock-cells = <1>;
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};
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};
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pinctrl: pinctrl@41000000 {
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compatible = "microchip,port-g1-pinctrl";
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#address-cells = <1>;

‎dts/bindings/clock/microchip/pic32cm_jh/microchip,pic32cm-jh-clock.yaml‎

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# Copyright (c) 2025 Microchip Technology Inc.
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# SPDX-License-Identifier: Apache-2.0
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title: Microchip PIC32CM_JH SOC family clock
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description: |
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Microchip PIC32CM_JH SOC family clock (OSCCTRL, OSC32KCTRL, GCLK, MCLK)
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include:
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- name: base.yaml
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- name: pinctrl-device.yaml
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compatible: "microchip,pic32cm-jh-clock"
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properties:
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on-timeout-ms:
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type: int
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default: 5
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description: |
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Timeout in milliseconds for clock to be on.
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Driver waits in clock on API to check if the clock is actually on,
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so that the waiting time is not indefinite.
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flash-wait-states:
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type: int
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default: 0
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description: |
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Number of wait states for a flash read operation.
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Change this value based on the NVM access time and system frequency
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up to 15 wait states.

‎dts/bindings/clock/microchip/pic32cm_jh/microchip,pic32cm-jh-fdpll.yaml‎

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# Copyright (c) 2025 Microchip Technology Inc.
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# SPDX-License-Identifier: Apache-2.0
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title: PIC32CM_JH FDPLL clock
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description: |
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Digital Phase Locked Loop (FDPLL), 48 MHz to 96 MHz output frequency from a 32 kHz to 2 MHz
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reference clock.
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include: [base.yaml]
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compatible: "microchip,pic32cm-jh-fdpll"
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properties:
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fdpll-on-demand-en:
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type: int
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enum:
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- 0
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- 1
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default: 0
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description: |
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0: The oscillator is always on
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1: The oscillator is running when a peripheral is requesting the oscillator to be used as a
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clock source. The oscillator is not running if no peripheral is requesting the clock source.
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Important: Initializing it with 1, along with clock enabled, can lead to indefinite wait
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for the clock to be on, if there is no peripheral request for the clock in the sequence of
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clock Initialization. If required, better to turn on the clock using API, instead of
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enabling both during startup.
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fdpll-run-in-standby-en:
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type: int
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enum:
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- 0
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- 1
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default: 1
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description: |
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0: The DPLLn is not running in standby sleep mode if no peripheral requests the clock.
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1: The DPLLn is running in standby sleep mode.
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If ONDEMAND is one, the DPLLn will be running when a peripheral is requesting the clock. If
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ONDEMAND is false, the clock source will always be running in standby sleep mode.
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fdpll-en:
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type: int
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enum:
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- 0
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- 1
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default: 0
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description: |
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Oscillator Enable
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0: to disable, 1: to enable
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fdpll-divider-ratio-frac:
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type: int
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default: 0
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description: |
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Set the fractional part of the frequency multiplier. (0 - 31)
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fdpll-divider-ratio-int:
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type: int
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default: 0
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description: |
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Set the integer part of the frequency multiplier. (0 - 4095)
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fdpll-xosc-clock-divider:
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type: int
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default: 0
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description: |
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Set the XOSC clock division factor (0 - 2047)
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fdpll-lock-bypass-en:
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type: int
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enum:
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- 0
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- 1
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default: 0
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description: |
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Lock Bypass
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0: to disable, 1: to enable
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fdpll-src:
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type: string
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enum:
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- "gclk0"
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- "gclk1"
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- "gclk2"
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- "gclk3"
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- "gclk4"
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- "gclk5"
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- "gclk6"
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- "gclk7"
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- "gclk8"
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- "xosc32k"
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- "xosc"
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default: "xosc32k"
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description: |
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Reference source clock selection
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fdpll-wakeup-fast-en:
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type: int
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enum:
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- 0
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- 1
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default: 0
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description: |
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Wake Up Fast
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0: to disable, 1: to enable
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fdpll-low-power-en:
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type: int
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enum:
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- 0
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- 1
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default: 0
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description: |
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When enabled, Time to Digital Converter is disabled (increase the output jitter).
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0: to disable, 1: to enable
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fdpll-pi-filter-type:
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type: string
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enum:
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- "default"
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- "low-bandwidth"
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- "high-bandwidth"
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- "high-damping"
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default: "default"
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description: |
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Proportional Integral Filter Selection
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fdpll-output-prescalar:
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type: string
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enum:
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- "div1"
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- "div2"
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- "div4"
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default: "div1"
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description: |
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Output prescalar divider.

‎dts/bindings/clock/microchip/pic32cm_jh/microchip,pic32cm-jh-gclkgen.yaml‎

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# Copyright (c) 2025 Microchip Technology Inc.
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# SPDX-License-Identifier: Apache-2.0
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title: PIC32CM_JH Generic clock generator
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description: |
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The Generic Clock controller (GCLK) features 9 Generic Clock Generators 0..8 that can
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provide a wide range of clock frequencies.
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include: [base.yaml]
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compatible: "microchip,pic32cm-jh-gclkgen"
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child-binding:
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properties:
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subsystem:
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type: int
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required: true
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description: |
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Clock subsystem
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gclkgen-div-factor:
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type: int
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default: 0
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description: |
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Represent a division value for the corresponding Generator. The actual division factor is
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dependent on the state of div-select (gclk1 0 - 65535, others 0 - 255)
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gclkgen-run-in-standby-en:
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type: int
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enum:
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- 0
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- 1
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default: 0
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description: |
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Keep the Generator running in Standby as long as it is configured to output to a dedicated
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GCLK_IOn pin. If output is not configured to a pin, this field has no effect and the
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generator will only be running if a peripheral requires the clock.
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0: to disable, 1: to enable
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gclkgen-div-select:
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type: string
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enum:
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- "div-factor"
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- "div-factor-power"
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default: "div-factor"
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description: |
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The Generator clock frequency equals the clock source frequency divided by div-factor
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DIV_FACTOR_POWER: The Generator clock frequency equals the clock source frequency divided
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by 2^(N+1), where N is the div-factor
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gclkgen-pin-output-en:
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type: int
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enum:
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- 0
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- 1
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default: 0
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description: |
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Generator clock output to the corresponding pin, if that pin is not configured as input
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source.
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0: to disable, 1: to enable
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gclkgen-pin-output-off-val:
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type: string
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enum:
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- "low"
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- "high"
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default: "low"
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description: |
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Output value of the corresponding pin, when the Generator is turned off or the output-en is
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false, as long as the pin is not source.
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gclkgen-improve-duty-cycle-en:
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type: int
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enum:
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- 0
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- 1
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default: 0
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description: |
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Improve the duty cycle of the Generator output to 50/50 for odd division factors
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0: to disable, 1: to enable
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gclkgen-en:
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type: int
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enum:
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- 0
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- 1
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default: 0
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description: |
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Enable gclk generator
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0: to disable, 1: to enable
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gclkgen-src:
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type: string
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enum:
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- "xosc"
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- "gclk-pin"
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- "gclk1"
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- "osculp32k"
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- "osc32k"
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- "xosc32k"
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- "osc48m"
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- "fdpll"
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default: "xosc"
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description: |
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Generator source clock selection
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gclkgen-pin-src-freq:
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type: int
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default: 0
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description: |
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External input clock frequency of the pin, when used as source. (0 - 200000000)

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