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22 | 22 | #include <zephyr/logging/log.h> |
23 | 23 |
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24 | 24 | #include "flash_stm32.h" |
25 | | -#include "stm32_hsem.h" |
26 | 25 |
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27 | 26 | LOG_MODULE_REGISTER(flash_stm32, CONFIG_FLASH_LOG_LEVEL); |
28 | 27 |
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@@ -59,32 +58,6 @@ int __weak flash_stm32_check_configuration(void) |
59 | 58 | return 0; |
60 | 59 | } |
61 | 60 |
|
62 | | -#if defined(CONFIG_MULTITHREADING) |
63 | | -/* |
64 | | - * This is named flash_stm32_sem_take instead of flash_stm32_lock (and |
65 | | - * similarly for flash_stm32_sem_give) to avoid confusion with locking |
66 | | - * actual flash pages. |
67 | | - */ |
68 | | -static inline void _flash_stm32_sem_take(const struct device *dev) |
69 | | -{ |
70 | | - k_sem_take(&FLASH_STM32_PRIV(dev)->sem, K_FOREVER); |
71 | | - z_stm32_hsem_lock(CFG_HW_FLASH_SEMID, HSEM_LOCK_WAIT_FOREVER); |
72 | | -} |
73 | | - |
74 | | -static inline void _flash_stm32_sem_give(const struct device *dev) |
75 | | -{ |
76 | | - z_stm32_hsem_unlock(CFG_HW_FLASH_SEMID); |
77 | | - k_sem_give(&FLASH_STM32_PRIV(dev)->sem); |
78 | | -} |
79 | | - |
80 | | -#define flash_stm32_sem_init(dev) k_sem_init(&FLASH_STM32_PRIV(dev)->sem, 1, 1) |
81 | | -#define flash_stm32_sem_take(dev) _flash_stm32_sem_take(dev) |
82 | | -#define flash_stm32_sem_give(dev) _flash_stm32_sem_give(dev) |
83 | | -#else |
84 | | -#define flash_stm32_sem_init(dev) |
85 | | -#define flash_stm32_sem_take(dev) |
86 | | -#define flash_stm32_sem_give(dev) |
87 | | -#endif |
88 | 61 |
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89 | 62 | #if !defined(CONFIG_SOC_SERIES_STM32WBX) |
90 | 63 | static int flash_stm32_check_status(const struct device *dev) |
@@ -319,7 +292,7 @@ int flash_stm32_option_bytes_lock(const struct device *dev, bool enable) |
319 | 292 | { |
320 | 293 | FLASH_TypeDef *regs = FLASH_STM32_REGS(dev); |
321 | 294 |
|
322 | | -#if defined(FLASH_OPTCR_OPTLOCK) /* F2, F4, F7 and H7 */ |
| 295 | +#if defined(FLASH_OPTCR_OPTLOCK) /* F2, F4, F7 */ |
323 | 296 | if (enable) { |
324 | 297 | regs->OPTCR |= FLASH_OPTCR_OPTLOCK; |
325 | 298 | } else if (regs->OPTCR & FLASH_OPTCR_OPTLOCK) { |
@@ -395,7 +368,7 @@ static int flash_stm32_control_register_disable(const struct device *dev) |
395 | 368 | { |
396 | 369 | FLASH_TypeDef *regs = FLASH_STM32_REGS(dev); |
397 | 370 |
|
398 | | -#if defined(FLASH_CR_LOCK) /* F0, F1, F2, F3, F4, F7, L4, G0, G4, H7, WB, WL \ |
| 371 | +#if defined(FLASH_CR_LOCK) /* F0, F1, F2, F3, F4, F7, L4, G0, G4, WB, WL \ |
399 | 372 | */ |
400 | 373 | /* |
401 | 374 | * Access to control register can be disabled by writing wrong key to |
@@ -425,7 +398,7 @@ static int flash_stm32_option_bytes_disable(const struct device *dev) |
425 | 398 | { |
426 | 399 | FLASH_TypeDef *regs = FLASH_STM32_REGS(dev); |
427 | 400 |
|
428 | | -#if defined(FLASH_OPTCR_OPTLOCK) /* F2, F4, F7 and H7 */ |
| 401 | +#if defined(FLASH_OPTCR_OPTLOCK) /* F2, F4, F7 */ |
429 | 402 | /* |
430 | 403 | * Access to option register can be disabled by writing wrong key to |
431 | 404 | * the key register. Option register will remain disabled until reset. |
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