dts: arm: st: stm32c0: add stm32c09x support

Add dts support for the STM32C091 and STM32C092 SoCs,
that are part of the STM32C0 series.

Signed-off-by: Thomas Stranger <[email protected]>

Author: str4t0m

dts/arm/st/c0/stm32c091.dtsi

@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2025 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/c0/stm32c071.dtsi>
+
+/* STM32C091 is a superset of the C071 with the exception of USB support.
+ * Since C071 provides the same set of peripheral as the C051,
+ * along with the addition of USB, once the C051 is introduced,
+ * it can be included instead, and the delete-node can be removed.
+ */
+/delete-node/ &usb;
+/delete-node/ &usb_fs_phy;
+
+/ {
+	soc {
+		compatible = "st,stm32c091", "st,stm32c0", "simple-bus";
+
+		timers15: timers@40014000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40014000 0x400>;
+			clocks = <&rcc STM32_CLOCK(APB1_2, 16)>;
+			resets = <&rctl STM32_RESET(APB1H, 16)>;
+			interrupts = <20 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				#pwm-cells = <3>;
+			};
+
+			counter {
+				compatible = "st,stm32-counter";
+				status = "disabled";
+			};
+		};
+
+		usart3: serial@40004800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004800 0x400>;
+			clocks = <&rcc STM32_CLOCK(APB1, 18)>;
+			resets = <&rctl STM32_RESET(APB1L, 18)>;
+			interrupts = <29 0>;
+			status = "disabled";
+		};
+
+		usart4: serial@40004c00 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004c00 0x400>;
+			clocks = <&rcc STM32_CLOCK(APB1, 19)>;
+			resets = <&rctl STM32_RESET(APB1L, 19)>;
+			interrupts = <29 0>;
+			status = "disabled";
+		};
+
+		dma1: dma@40020000 {
+			interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>;
+			dma-requests = <7>;
+		};
+
+		dmamux1: dmamux@40020800 {
+			dma-channels = <7>;
+			dma-requests = <53>;
+		};
+	};
+};

dts/arm/st/c0/stm32c091Xb.dtsi

@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2024 STMicroelectronics
+ * Copyright (c) 2025 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/c0/stm32c091.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(36)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(128)>;
+			};
+		};
+	};
+};

dts/arm/st/c0/stm32c091Xc.dtsi

@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2024 STMicroelectronics
+ * Copyright (c) 2025 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/c0/stm32c091.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(36)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(256)>;
+			};
+		};
+	};
+};

dts/arm/st/c0/stm32c092.dtsi

@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2025 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/c0/stm32c091.dtsi>
+
+/ {
+	soc {
+		compatible = "st,stm32c092", "st,stm32c0", "simple-bus";
+
+		fdcan1: can@40006400 {
+			compatible = "st,stm32-fdcan";
+			reg = <0x40006400 0x400>, <0x4000b400 0x350>;
+			reg-names = "m_can", "message_ram";
+			interrupts = <30 0>, <31 0>;
+			interrupt-names = "int0", "int1";
+			clocks = <&rcc STM32_CLOCK(APB1, 12)>;
+			bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>;
+			status = "disabled";
+		};
+	};
+};

dts/arm/st/c0/stm32c092Xb.dtsi

@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2024 STMicroelectronics
+ * Copyright (c) 2025 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/c0/stm32c092.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(30)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(128)>;
+			};
+		};
+	};
+};

dts/arm/st/c0/stm32c092Xc.dtsi

@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2024 STMicroelectronics
+ * Copyright (c) 2025 Thomas Stranger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/c0/stm32c092.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(30)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(256)>;
+			};
+		};
+	};
+};