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GTLin08cfriedt
GTLin08
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drivers/espi: ite: Add support for ESPI_PERIPHERAL_HOST_IO_PVT
Add support the host I/O over eSPI peripheral channel for private channel. The default port number of ESPI_PERIPHERAL_HOST_IO_PVT_PORT_NUM for ITE SoC is 0x68. Signed-off-by: Tim Lin <[email protected]>
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6 files changed

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‎drivers/espi/Kconfig.it8xxx2

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,12 @@ config ESPI_PERIPHERAL_8042_KBC
2020
config ESPI_PERIPHERAL_HOST_IO
2121
default y
2222

23+
config ESPI_PERIPHERAL_HOST_IO_PVT
24+
default y
25+
26+
config ESPI_PERIPHERAL_HOST_IO_PVT_PORT_NUM
27+
default 0x0068
28+
2329
config ESPI_PERIPHERAL_DEBUG_PORT_80
2430
default y
2531

‎drivers/espi/espi_it8xxx2.c

Lines changed: 80 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,7 @@ LOG_MODULE_REGISTER(espi, CONFIG_ESPI_LOG_LEVEL);
3232
#define IT8XXX2_PORT_80_IRQ DT_INST_IRQ_BY_IDX(0, 5, irq)
3333
#define IT8XXX2_PMC2_IBF_IRQ DT_INST_IRQ_BY_IDX(0, 6, irq)
3434
#define IT8XXX2_TRANS_IRQ DT_INST_IRQ_BY_IDX(0, 7, irq)
35+
#define IT8XXX2_PMC3_IBF_IRQ DT_INST_IRQ_BY_IDX(0, 8, irq)
3536

3637
/* General Capabilities and Configuration 1 */
3738
#define IT8XXX2_ESPI_MAX_FREQ_MASK GENMASK(2, 0)
@@ -306,8 +307,20 @@ struct pmc_regs {
306307
volatile uint8_t MBXCTRL;
307308
/* 0x1a-0x1f: Reserved2 */
308309
volatile uint8_t reserved2[6];
309-
/* 0x20-0xff: Reserved3 */
310-
volatile uint8_t reserved3[0xe0];
310+
/* 0x20: Host Interface PM Channel 3 Status */
311+
volatile uint8_t PM3STS;
312+
/* 0x21: Host Interface PM Channel 3 Data Out Port */
313+
volatile uint8_t PM3DO;
314+
/* 0x22: Host Interface PM Channel 3 Data In Port */
315+
volatile uint8_t PM3DI;
316+
/* 0x23: Host Interface PM Channel 3 Control */
317+
volatile uint8_t PM3CTL;
318+
/* 0x24: Host Interface PM Channel 3 Interrupt Control */
319+
volatile uint8_t PM3IC;
320+
/* 0x25: Host Interface PM Channel 3 Interrupt Enable */
321+
volatile uint8_t PM3IE;
322+
/* 0x26-0xff: Reserved3 */
323+
volatile uint8_t reserved3[0xda];
311324
};
312325

313326
/* Input Buffer Full Interrupt Enable */
@@ -325,6 +338,8 @@ struct pmc_regs {
325338
#define PMC_PM2CTL_IBFIE BIT(0)
326339
/* General Purpose Flag */
327340
#define PMC_PM2STS_GPF BIT(2)
341+
/* PMC3 Input Buffer Full Interrupt Enable */
342+
#define PMC_PM3CTL_IBFIE BIT(0)
328343

329344
/*
330345
* Dedicated Interrupt
@@ -614,6 +629,12 @@ IT8XXX2_ESPI_REG_OFFSET_CHECK(pmc_regs, PM2DO, 0x11);
614629
IT8XXX2_ESPI_REG_OFFSET_CHECK(pmc_regs, PM2DI, 0x14);
615630
IT8XXX2_ESPI_REG_OFFSET_CHECK(pmc_regs, PM2CTL, 0x16);
616631
IT8XXX2_ESPI_REG_OFFSET_CHECK(pmc_regs, MBXCTRL, 0x19);
632+
IT8XXX2_ESPI_REG_OFFSET_CHECK(pmc_regs, PM3STS, 0x20);
633+
IT8XXX2_ESPI_REG_OFFSET_CHECK(pmc_regs, PM3DO, 0x21);
634+
IT8XXX2_ESPI_REG_OFFSET_CHECK(pmc_regs, PM3DI, 0x22);
635+
IT8XXX2_ESPI_REG_OFFSET_CHECK(pmc_regs, PM3CTL, 0x23);
636+
IT8XXX2_ESPI_REG_OFFSET_CHECK(pmc_regs, PM3IC, 0x24);
637+
IT8XXX2_ESPI_REG_OFFSET_CHECK(pmc_regs, PM3IE, 0x25);
617638

618639
/* eSPI slave register structure check */
619640
IT8XXX2_ESPI_REG_SIZE_CHECK(espi_slave_regs, 0xd8);
@@ -753,6 +774,29 @@ static const struct ec2i_t pmc1_settings[] = {
753774
{HOST_INDEX_LDA, 0x01},
754775
};
755776

777+
#ifdef CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT
778+
#define IT8XXX2_ESPI_HOST_IO_PVT_DATA_PORT_MSB \
779+
((CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT_PORT_NUM >> 8) & 0xff)
780+
#define IT8XXX2_ESPI_HOST_IO_PVT_DATA_PORT_LSB (CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT_PORT_NUM & 0xff)
781+
#define IT8XXX2_ESPI_HOST_IO_PVT_CMD_PORT_MSB \
782+
(((CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT_PORT_NUM + 4) >> 8) & 0xff)
783+
#define IT8XXX2_ESPI_HOST_IO_PVT_CMD_PORT_LSB \
784+
((CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT_PORT_NUM + 4) & 0xff)
785+
static const struct ec2i_t pmc3_settings[] = {
786+
/* Select logical device 17h(PMC3) */
787+
{HOST_INDEX_LDN, LDN_PMC3},
788+
/* I/O Port Base Address (data/command ports) */
789+
{HOST_INDEX_IOBAD0_MSB, IT8XXX2_ESPI_HOST_IO_PVT_DATA_PORT_MSB},
790+
{HOST_INDEX_IOBAD0_LSB, IT8XXX2_ESPI_HOST_IO_PVT_DATA_PORT_LSB},
791+
{HOST_INDEX_IOBAD1_MSB, IT8XXX2_ESPI_HOST_IO_PVT_CMD_PORT_MSB},
792+
{HOST_INDEX_IOBAD1_LSB, IT8XXX2_ESPI_HOST_IO_PVT_CMD_PORT_LSB},
793+
/* Set IRQ=00h for logical device */
794+
{HOST_INDEX_IRQNUMX, 0x00},
795+
/* Enable logical device */
796+
{HOST_INDEX_LDA, 0x01},
797+
};
798+
#endif
799+
756800
#ifdef CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD
757801
#define IT8XXX2_ESPI_HC_DATA_PORT_MSB \
758802
((CONFIG_ESPI_PERIPHERAL_HOST_CMD_DATA_PORT_NUM >> 8) & 0xff)
@@ -960,6 +1004,9 @@ static void pnpcfg_it8xxx2_init(const struct device *dev)
9601004
#ifdef CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD
9611005
PNPCFG(pmc2);
9621006
#endif
1007+
#ifdef CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT
1008+
PNPCFG(pmc3);
1009+
#endif
9631010
#if defined(CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD) || \
9641011
defined(CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION)
9651012
PNPCFG(smfi);
@@ -1178,6 +1225,33 @@ static void pmc2_it8xxx2_init(const struct device *dev)
11781225
}
11791226
#endif
11801227

1228+
#ifdef CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT
1229+
/* PMC3 (Host private port) */
1230+
static void pmc3_it8xxx2_ibf_isr(const struct device *dev)
1231+
{
1232+
const struct espi_it8xxx2_config *const config = dev->config;
1233+
struct espi_it8xxx2_data *const data = dev->data;
1234+
struct pmc_regs *const pmc_reg = (struct pmc_regs *)config->base_pmc;
1235+
struct espi_event evt = {.evt_type = ESPI_BUS_PERIPHERAL_NOTIFICATION,
1236+
.evt_details = ESPI_PERIPHERAL_HOST_IO_PVT,
1237+
.evt_data = ESPI_PERIPHERAL_NODATA};
1238+
1239+
evt.evt_data = pmc_reg->PM3DI;
1240+
espi_send_callbacks(&data->callbacks, dev, evt);
1241+
}
1242+
1243+
static void pmc3_it8xxx2_init(const struct device *dev)
1244+
{
1245+
const struct espi_it8xxx2_config *const config = dev->config;
1246+
struct pmc_regs *const pmc_reg = (struct pmc_regs *)config->base_pmc;
1247+
1248+
/* Enable pmc3 input buffer full interrupt */
1249+
pmc_reg->PM3CTL |= PMC_PM3CTL_IBFIE;
1250+
IRQ_CONNECT(IT8XXX2_PMC3_IBF_IRQ, 0, pmc3_it8xxx2_ibf_isr, DEVICE_DT_INST_GET(0), 0);
1251+
irq_enable(IT8XXX2_PMC3_IBF_IRQ);
1252+
}
1253+
#endif
1254+
11811255
#define IT8XXX2_ESPI_VW_SEND_TIMEOUT_US (USEC_PER_MSEC * 10)
11821256

11831257
/* eSPI api functions */
@@ -2539,6 +2613,10 @@ static int espi_it8xxx2_init(const struct device *dev)
25392613
/* enable pmc2 for host command port */
25402614
pmc2_it8xxx2_init(dev);
25412615
#endif
2616+
#ifdef CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT
2617+
/* enable pmc3 for host private port */
2618+
pmc3_it8xxx2_init(dev);
2619+
#endif
25422620

25432621
/* Reset vwidx_cached_flag[] at initialization */
25442622
espi_it8xxx2_reset_vwidx_cache(dev);

‎dts/riscv/ite/it51xxx.dtsi

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1237,7 +1237,8 @@
12371237
IT51XXX_IRQ_PMC1_IBF IRQ_TYPE_LEVEL_HIGH
12381238
IT51XXX_IRQ_PCH_P80 IRQ_TYPE_LEVEL_HIGH
12391239
IT51XXX_IRQ_PMC2_IBF IRQ_TYPE_LEVEL_HIGH
1240-
IT51XXX_IRQ_WKINTD IRQ_TYPE_LEVEL_HIGH>;
1240+
IT51XXX_IRQ_WKINTD IRQ_TYPE_LEVEL_HIGH
1241+
IT51XXX_IRQ_PMC3_IBF IRQ_TYPE_LEVEL_HIGH>;
12411242
interrupt-parent = <&intc>;
12421243
wucctrl = <&wuc_wu42>;
12431244
#address-cells = <1>;

‎dts/riscv/ite/it8xxx2.dtsi

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -441,7 +441,8 @@
441441
IT8XXX2_IRQ_PMC1_IBF IRQ_TYPE_LEVEL_HIGH
442442
IT8XXX2_IRQ_PCH_P80 IRQ_TYPE_LEVEL_HIGH
443443
IT8XXX2_IRQ_PMC2_IBF IRQ_TYPE_LEVEL_HIGH
444-
IT8XXX2_IRQ_WKINTD IRQ_TYPE_LEVEL_HIGH>;
444+
IT8XXX2_IRQ_WKINTD IRQ_TYPE_LEVEL_HIGH
445+
IT8XXX2_IRQ_PMC3_IBF IRQ_TYPE_LEVEL_HIGH>;
445446
interrupt-parent = <&intc>;
446447
wucctrl = <&wuc_wu42>;
447448
#address-cells = <1>;

‎include/zephyr/dt-bindings/interrupt-controller/ite-intc.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -57,6 +57,8 @@
5757
#define IT8XXX2_IRQ_WU67 55
5858
/* Group 7 */
5959
#define IT8XXX2_IRQ_TIMER2 58
60+
/* Group 8 */
61+
#define IT8XXX2_IRQ_PMC3_IBF 67
6062
/* Group 9 */
6163
#define IT8XXX2_IRQ_WU70 72
6264
#define IT8XXX2_IRQ_WU71 73

‎include/zephyr/dt-bindings/interrupt-controller/ite-it51xxx-intc.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -59,6 +59,8 @@
5959
#define IT51XXX_IRQ_WU67 55
6060
/* Group 7 */
6161
#define IT51XXX_IRQ_TIMER2 58
62+
/* Group 8 */
63+
#define IT51XXX_IRQ_PMC3_IBF 67
6264
/* Group 9 */
6365
#define IT51XXX_IRQ_WU70 72
6466
#define IT51XXX_IRQ_WU71 73

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