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drivers: pinctrl: add iopctl driver for RT 3 digital platforms
RT3 digital platforms won't reuse lpc_iocon driver, new iopctl driver have been developed for iopctl IP. Due to RT700 have multi iopctl instances, add code to handle the index value recorded in new pinctrl header file Signed-off-by: Lucien Zhao <[email protected]>
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‎doc/releases/migration-guide-4.1.rst‎

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@@ -39,6 +39,27 @@ LVGL
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Device Drivers and Devicetree
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*****************************
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* The :dtcompatible: ``nxp,lpc-iocon`` and ``nxp,rt-iocon-pinctrl`` driver won't be used
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for RT 3 digital platforms.
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New :dtcompatible:`nxp,iopctl` and :dtcompatible:`nxp,rt-iopctl-pinctrl` have been created
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for iopctl IP on RT 3 digital platforms. Change iocon node to iopctl0 node on RT500/600
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platforms. New pinctrl model add instance index parameter in pin header files, however,
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for the application layer, the pin macro name will not change. So it means application
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layer won't be affected by changes in the driver layer.(:github:`81086`)
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example:
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.. code-block:: devicetree
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/ {
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iopctl0: iopctl@4000 {
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compatible = "nxp,iopctl";
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reg = <0x4000 0x1000>;
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status = "okay";
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pinctrl: pinctrl {
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compatible = "nxp,rt-iopctl-pinctrl";
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};
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};
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Controller Area Network (CAN)
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=============================
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‎drivers/pinctrl/CMakeLists.txt‎

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@@ -20,6 +20,7 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_MCHP_XEC pinctrl_mchp_xec.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_IMX pinctrl_imx.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_SIFIVE pinctrl_sifive.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_IOCON pinctrl_lpc_iocon.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_IOPCTL pinctrl_iopctl.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_CC13XX_CC26XX pinctrl_cc13xx_cc26xx.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_ESP32 pinctrl_esp32.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_RV32M1 pinctrl_rv32m1.c)

‎drivers/pinctrl/Kconfig‎

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@@ -49,6 +49,7 @@ source "drivers/pinctrl/Kconfig.xec"
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source "drivers/pinctrl/Kconfig.imx"
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source "drivers/pinctrl/Kconfig.sifive"
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source "drivers/pinctrl/Kconfig.lpc_iocon"
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source "drivers/pinctrl/Kconfig.iopctl"
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source "drivers/pinctrl/Kconfig.cc13xx_cc26xx"
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source "drivers/pinctrl/Kconfig.esp32"
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source "drivers/pinctrl/Kconfig.rv32m1"

‎drivers/pinctrl/Kconfig.iopctl‎

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# Copyright 2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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config PINCTRL_NXP_IOPCTL
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bool "IOPCTL Pin controller driver for NXP MCUs"
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default y
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depends on DT_HAS_NXP_RT_IOPCTL_PINCTRL_ENABLED
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help
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Enable pin controller driver for NXP MCUs

‎drivers/pinctrl/Kconfig.lpc_iocon‎

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# Copyright 2022, NXP
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# Copyright 2022,2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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config PINCTRL_NXP_IOCON
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bool "IOCON Pin controller driver for NXP LPC MCUs"
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default y
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depends on DT_HAS_NXP_LPC_IOCON_PINCTRL_ENABLED || \
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DT_HAS_NXP_LPC11U6X_PINCTRL_ENABLED || \
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DT_HAS_NXP_RT_IOCON_PINCTRL_ENABLED
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DT_HAS_NXP_LPC11U6X_PINCTRL_ENABLED
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help
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Enable pin controller driver for NXP LPC MCUs

‎drivers/pinctrl/pinctrl_iopctl.c‎

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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_iopctl
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/init.h>
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#define OFFSET(mux) (((mux) & 0xFFF00000) >> 20)
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#define INDEX(mux) (((mux) & 0xF0000) >> 16)
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#define Z_PINCTRL_IOPCTL_PIN_MASK 0xFFF
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/* IOPCTL register addresses. */
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static uint32_t *iopctl[] = {
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#if (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(iopctl0)))
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(uint32_t *)DT_REG_ADDR(DT_NODELABEL(iopctl0)),
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#else
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NULL,
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#endif
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#if (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(iopctl1)))
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(uint32_t *)DT_REG_ADDR(DT_NODELABEL(iopctl1)),
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#else
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NULL,
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#endif
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#if (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(iopctl2)))
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(uint32_t *)DT_REG_ADDR(DT_NODELABEL(iopctl2)),
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#else
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NULL,
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#endif
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};
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
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{
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for (uint8_t i = 0; i < pin_cnt; i++) {
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uint32_t pin_mux = pins[i];
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uint32_t index = INDEX(pin_mux);
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uint32_t offset = OFFSET(pin_mux);
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if (index < ARRAY_SIZE(iopctl)) {
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/* Set pinmux */
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*(iopctl[index] + offset) = (pin_mux & Z_PINCTRL_IOPCTL_PIN_MASK);
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} else {
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return -EINVAL;
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}
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}
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return 0;
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}

‎dts/bindings/pinctrl/nxp,iopctl.yaml‎

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# Copyright 2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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description: IO PAD Controller (IOPCTL)
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compatible: "nxp,iopctl"
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include: base.yaml
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properties:
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reg:
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required: true

‎dts/bindings/pinctrl/nxp,rt-iocon-pinctrl.yaml‎ renamed to ‎dts/bindings/pinctrl/nxp,rt-iopctl-pinctrl.yaml‎

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# Copyright 2022, NXP
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# Copyright 2022,2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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description: |
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RT600/RT500 pin control node. This node defines pin configurations in pin
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RT700/RT600/RT500 pin control node. This node defines pin configurations in pin
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groups, and has the 'pinctrl' node identifier in the SOC's devicetree. Each
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group within the pin configuration defines a peripheral's pin configuration.
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Each numbered subgroup represents pins with shared configuration for that
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If only the required properties are supplied, the ICON_PIO register will
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be assigned the following values:
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IOCON_FUNC=<pin mux selection>,
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IOCON_PUPDENA = 0,
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IOCON_PUPDSEL = 0,
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IOCON_IBENA = 0,
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IOCON_SLEWRATE = <slew-rate selection>,
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IOCON_FULLDRIVE = <drive-strength selection>,
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IOCON_AMENA = 0,
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IOCON_ODENA = 0,
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IOCON_IIENA = 0,
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IOPCTL_FUNC=<pin mux selection>,
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IOPCTL_PUPDENA = 0,
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IOPCTL_PUPDSEL = 0,
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IOPCTL_IBENA = 0,
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IOPCTL_SLEWRATE = <slew-rate selection>,
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IOPCTL_FULLDRIVE = <drive-strength selection>,
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IOPCTL_AMENA = 0,
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IOPCTL_ODENA = 0,
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IOPCTL_IIENA = 0,
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Note the inherited pinctrl properties defined below have the following effects:
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drive-open-drain: IOCON_ODENA=1
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bias-pull-up: IOCON_PUPDENA=1, IOCON_PUPSEL=1
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bias-pull-down: IOCON_PUPDENA=1, IOCON_PUPSEL=0
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input-enable: IOCON_IBENA=1
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drive-open-drain: IOPCTL_ODENA=1
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bias-pull-up: IOPCTL_PUPDENA=1, IOPCTL_PUPSEL=1
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bias-pull-down: IOPCTL_PUPDENA=1, IOPCTL_PUPSEL=0
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input-enable: IOPCTL_IBENA=1
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compatible: "nxp,rt-iocon-pinctrl"
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compatible: "nxp,rt-iopctl-pinctrl"
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include: base.yaml
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child-binding:
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description: iMX RT IOCON pin controller pin group
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description: iMX RT IOPCTL pin controller pin group
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child-binding:
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description: |
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iMX RT IOCON pin controller pin configuration node
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iMX RT IOPCTL pin controller pin configuration node
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include:
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- name: pincfg-node.yaml
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- "normal"
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- "slow"
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description: |
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Pin output slew rate. Sets the SLEWRATE field in the IOCON register.
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Pin output slew rate. Sets the SLEWRATE field in the IOPCTL register.
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0 SLEWRATE_0- normal mode, output slew rate is standard
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1 SLEWRATE_1- slow mode, output slew rate is slower
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drive-strength:
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- "high"
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description: |
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Pin output drive strength. Sets the FULLDRIVE field in the
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IOCON register.
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IOPCTL register.
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0 FULLDRIVE_0- Normal output drive mode
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1 FULLDRIVE_1- Full output drive mode, output strength is twice
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the drive strength of normal drive mode.

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