Skip to content

Commit 4004665

Browse files
cwshuioannisg
authored andcommitted
arch: riscv: linker: fix _image_rom_start symbol
Change _image_rom_start symbol from 0 to the beginning of ROMABLE_REGION. Signed-off-by: Jim Shu <[email protected]>
1 parent dfa52a3 commit 4004665

File tree

1 file changed

+23
-14
lines changed

1 file changed

+23
-14
lines changed

include/arch/riscv/common/linker.ld

Lines changed: 23 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,27 @@
3131
#define _EXCEPTION_SECTION_NAME exceptions
3232
#define _RESET_SECTION_NAME reset
3333

34+
#ifdef CONFIG_XIP
35+
#if DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), soc_nv_flash, okay)
36+
#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))
37+
#define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
38+
#elif DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), jedec_spi_nor, okay)
39+
/* For jedec,spi-nor we expect the spi controller to memory map the flash
40+
* and for that mapping to be the second register property of the spi
41+
* controller.
42+
*/
43+
#define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))
44+
#define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)
45+
#define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)
46+
#endif
47+
#else /* CONFIG_XIP */
48+
#define ROM_BASE CONFIG_SRAM_BASE_ADDRESS
49+
#define ROM_SIZE KB(CONFIG_SRAM_SIZE)
50+
#endif /* CONFIG_XIP */
51+
52+
#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS
53+
#define RAM_SIZE KB(CONFIG_SRAM_SIZE)
54+
3455
#ifdef CONFIG_RISCV_PMP
3556
#define MPU_MIN_SIZE 4
3657
#define MPU_MIN_SIZE_ALIGN . = ALIGN(MPU_MIN_SIZE );
@@ -50,21 +71,9 @@
5071
MEMORY
5172
{
5273
#ifdef CONFIG_XIP
53-
#if DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), soc_nv_flash, okay)
54-
#define ROM_BASE DT_REG_ADDR(DT_CHOSEN(zephyr_flash))
55-
#define ROM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
56-
#elif DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), jedec_spi_nor, okay)
57-
/* For jedec,spi-nor we expect the spi controller to memory map the flash
58-
* and for that mapping to be the second register property of the spi
59-
* controller.
60-
*/
61-
#define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))
62-
#define ROM_BASE DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)
63-
#define ROM_SIZE DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)
64-
#endif
6574
ROM (rx) : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE
6675
#endif
67-
RAM (rwx) : ORIGIN = CONFIG_SRAM_BASE_ADDRESS, LENGTH = KB(CONFIG_SRAM_SIZE)
76+
RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE
6877
/* Used by and documented in include/linker/intlist.ld */
6978
IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
7079
}
@@ -91,7 +100,7 @@ SECTIONS
91100
}
92101

93102
GROUP_START(ROMABLE_REGION)
94-
_image_rom_start = .;
103+
_image_rom_start = ROM_BASE;
95104

96105
SECTION_PROLOGUE(_VECTOR_SECTION_NAME,,)
97106
{

0 commit comments

Comments
 (0)