dts: i2s: add i2s node for max32655fthr

- add basic dma only i2s dts binding for max32-i2s
- add i2s node with default config to max32655.dtsi
- add i2s pin definition for max32655fthr board as per spec

Signed-off-by: Anuj Pathak <[email protected]>

Author: cx-anuj-pathak

boards/adi/max32655fthr/max32655fthr_max32655_m4.dts

@@ -154,6 +154,12 @@
 	status = "okay";
 };
 
+&i2s0 {
+	status = "okay";
+	pinctrl-0 = <&i2s_sck_p1_2 &i2s_ws_p1_3 &i2s_sdi_p1_4 &i2s_sdo_p1_5>;
+	pinctrl-names = "default";
+};
+
 &wdt0 {
 	status = "okay";
 };

dts/arm/adi/max32/max32655.dtsi

@@ -164,5 +164,23 @@
 				status = "disabled";
 			};
 		};
+
+		i2s0: i2s0@40060000 {
+			compatible = "adi,max32-i2s";
+			reg = <0x40060000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			/*
+			 * DMA Configuration is provided as an example.
+			 * user is free to change dma channel index,
+			 * but tx and rx slot should be kept same as below
+			 *
+			 * ref to MAX32655 User Guide
+			 * Table 9-2: DMA Source and Destination by Peripheral
+			 */
+			dmas = <&dma0 0 MAX32_DMA_SLOT_I2S_TX>, <&dma0 1 MAX32_DMA_SLOT_I2S_RX>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
 	};
 };

dts/bindings/i2s/adi,max32-i2s.yaml

@@ -0,0 +1,34 @@
+# Copyright (c) 2025 Croxel Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Analog Devices MAX32 series I2S controller
+
+compatible: "adi,max32-i2s"
+
+include: [i2s-controller.yaml, pinctrl-device.yaml]
+
+properties:
+  reg:
+    required: true
+
+  dmas:
+    required: true
+    description: |
+      DMA channels for RX and TX. Two channels must be provided in the following order:
+      - RX DMA channel
+      - TX DMA channel
+
+  dma-names:
+    required: true
+    description: |
+      Names of DMA channels for RX and TX. Must be provided in the following order:
+      - rx
+      - tx
+
+  i2s-clk-frequency:
+    type: int
+    default: 12288000
+    description: |
+      Frequency of the I2S clock in Hz.
+      This clock is used to derive the bit clock and frame clock.
+      Default to 12.288 MHz, which is suitable for common audio sample rates.

include/zephyr/dt-bindings/dma/max32655_dma.h

@@ -18,6 +18,7 @@
 #define MAX32_DMA_SLOT_UART2_RX 0x0EU
 #define MAX32_DMA_SLOT_SPI0_RX  0x0FU
 #define MAX32_DMA_SLOT_UART3_RX 0x1CU
+#define MAX32_DMA_SLOT_I2S_RX   0x1EU
 #define MAX32_DMA_SLOT_SPI1_TX  0x21U
 #define MAX32_DMA_SLOT_UART0_TX 0x24U
 #define MAX32_DMA_SLOT_UART1_TX 0x25U
@@ -28,6 +29,6 @@
 #define MAX32_DMA_SLOT_UART2_TX 0x2EU
 #define MAX32_DMA_SLOT_SPI0_TX  0x2FU
 #define MAX32_DMA_SLOT_UART3_TX 0x3CU
-#define MAX32_DMA_SLOT_I2S      0x3EU
+#define MAX32_DMA_SLOT_I2S_TX   0x3EU
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32655_DMA_H_ */