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Use TX FIFO level interrupt if available in hardware. It matches the
Zephyr UART API and avoids "bootstrapping" which is needed when using
the TX edge interrupt ("TI"). TX FIFO has room for up to 32 characters
and will typically reduce the number of interrupts.
Details:
APBUART can be synthesized with or without support for TX/RX FIFO.
Edge interrupts which fire when TX holding register changes and RX data
available are always available, independent of the FIFO configuration.
If FIFO is made available at synthesis time, two additional interrupts
become available: TX FIFO half-empty and RX FIFO half-full. These
are level interrupts.
Signed-off-by: Martin Åberg <[email protected]>
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