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soc: renesas: Add initial support for RA4M3 SOC
Initial commit to support Renesas RA4M3 SOC Signed-off-by: Quy Tran <[email protected]>
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‎dts/arm/renesas/ra/ra4/r7fa4m3af3cfb.dtsi‎

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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/clock/ra_clock.h>
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#include <arm/renesas/ra/ra4/r7fa4m3ax.dtsi>
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/ {
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soc {
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flash-controller@407e0000 {
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reg = <0x407e0000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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reg = <0x0 DT_SIZE_M(1)>;
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};
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};
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};
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};

‎dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi‎

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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/renesas/ra/ra4/ra4-cm33-common.dtsi>
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#include <zephyr/dt-bindings/clock/ra_clock.h>
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/ {
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soc {
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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reg = <0x20000000 DT_SIZE_K(128)>;
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};
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ioport6: gpio@400800c0 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x400800c0 0x20>;
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port = <6>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport7: gpio@400800e0 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x400800e0 0x20>;
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port = <7>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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ioport8: gpio@40080100 {
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compatible = "renesas,ra-gpio-ioport";
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reg = <0x40080100 0x20>;
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port = <8>;
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <16>;
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status = "disabled";
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};
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sci1: sci1@40118100 {
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compatible = "renesas,ra-sci";
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interrupts = <4 1>, <5 1>, <6 1>, <7 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40118100 0x100>;
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clocks = <&pclka MSTPB 30>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <1>;
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status = "disabled";
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};
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};
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sci2: sci2@40118200 {
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compatible = "renesas,ra-sci";
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interrupts = <8 1>, <9 1>, <10 1>, <11 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40118200 0x100>;
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clocks = <&pclka MSTPB 29>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <2>;
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status = "disabled";
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};
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};
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sci3: sci3@40118300 {
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compatible = "renesas,ra-sci";
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interrupts = <12 1>, <13 1>, <14 1>, <15 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40118300 0x100>;
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clocks = <&pclka MSTPB 28>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <3>;
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status = "disabled";
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};
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};
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sci4: sci4@40118400 {
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compatible = "renesas,ra-sci";
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interrupts = <16 1>, <17 1>, <18 1>, <19 1>;
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interrupt-names = "rxi", "txi", "tei", "eri";
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reg = <0x40118400 0x100>;
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clocks = <&pclka MSTPB 27>;
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status = "disabled";
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uart {
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compatible = "renesas,ra-sci-uart";
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channel = <4>;
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status = "disabled";
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};
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};
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};
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clocks: clocks {
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xtal: clock-xtal {
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compatible = "renesas,ra-cgc-external-clock";
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clock-frequency = <DT_FREQ_M(24)>;
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#clock-cells = <0>;
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status = "disabled";
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};
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hoco: clock-hoco {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(20)>;
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#clock-cells = <0>;
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};
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moco: clock-moco {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(8)>;
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#clock-cells = <0>;
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};
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loco: clock-loco {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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};
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subclk: clock-subclk {
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compatible = "renesas,ra-cgc-subclk";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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status = "disabled";
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};
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pll: pll {
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compatible = "renesas,ra-cgc-pll";
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#clock-cells = <0>;
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/* PLL */
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source = <RA_PLL_SOURCE_MAIN_OSC>;
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div = <RA_PLL_DIV_3>;
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mul = <25 0>;
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status = "disabled";
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freq = <DT_FREQ_M(200)>;
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};
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pll2: pll2 {
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compatible = "renesas,ra-cgc-pll";
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#clock-cells = <0>;
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source = <RA_PLL_SOURCE_DISABLE>;
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div = <RA_PLL_DIV_2>;
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mul = <20 0>;
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status = "disabled";
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};
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pclkblock: pclkblock {
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compatible = "renesas,ra-cgc-pclk-block";
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#clock-cells = <0>;
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sysclock-src = <RA_CLOCK_SOURCE_PLL>;
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status = "okay";
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iclk: iclk {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_2>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclka: pclka {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_2>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclkb: pclkb {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_4>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclkc: pclkc {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_4>;
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#clock-cells = <2>;
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status = "okay";
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};
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pclkd: pclkd {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_2>;
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#clock-cells = <2>;
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status = "okay";
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};
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fclk: fclk {
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compatible = "renesas,ra-cgc-pclk";
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clk_div = <RA_SYS_CLOCK_DIV_4>;
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#clock-cells = <2>;
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status = "okay";
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};
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clkout: clkout {
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compatible = "renesas,ra-cgc-pclk";
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#clock-cells = <2>;
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status = "disabled";
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};
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uclk: uclk {
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compatible = "renesas,ra-cgc-pclk";
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#clock-cells = <2>;
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status = "disabled";
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};
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};
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};
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};

‎soc/renesas/ra/ra4m3/CMakeLists.txt‎

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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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zephyr_include_directories(.)
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zephyr_sources(
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soc.c
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)
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zephyr_linker_sources(SECTIONS sections.ld)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

‎soc/renesas/ra/ra4m3/Kconfig‎

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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_RA4M3
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select ARM
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select CPU_HAS_ARM_MPU
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select CPU_CORTEX_M33
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select HAS_RENESAS_RA_FSP
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select CPU_CORTEX_M_HAS_DWT
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select ARMV8_M_DSP
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select CPU_HAS_FPU
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select FPU
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select HAS_SWO
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select XIP

‎soc/renesas/ra/ra4m3/Kconfig.defconfig‎

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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_RA4M3
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config NUM_IRQS
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default 96
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config PINCTRL
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default y
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endif # SOC_SERIES_RA4M3

‎soc/renesas/ra/ra4m3/Kconfig.soc‎

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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_RA4M3
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bool
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select SOC_FAMILY_RENESAS_RA
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help
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Renesas RA4M3 series
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config SOC_R7FA4M3AF3CFB
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bool
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select SOC_SERIES_RA4M3
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help
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R7FA4M3AF3CFB
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config SOC_SERIES
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default "ra4m3" if SOC_SERIES_RA4M3
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config SOC
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default "r7fa4m3af3cfb" if SOC_R7FA4M3AF3CFB

‎soc/renesas/ra/ra4m3/sections.ld‎

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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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.code_in_ram :
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{
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. = ALIGN(4);
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__Code_In_RAM_Start = .;
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KEEP(*(.code_in_ram*))
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__Code_In_RAM_End = .;
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} > RAMABLE_REGION
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SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
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{
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/* If DTC is used, put the DTC vector table at the start of SRAM.
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This avoids memory holes due to 1K alignment required by it. */
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*(.fsp_dtc_vector_table)
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} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
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SECTION_PROLOGUE(.option_setting_ofs,,)
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{
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__OPTION_SETTING_OFS_Start = .;
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KEEP(*(.option_setting_ofs0))
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. = __OPTION_SETTING_OFS_Start + 0x04;
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KEEP(*(.option_setting_ofs2))
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. = __OPTION_SETTING_OFS_Start + 0x10;
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KEEP(*(.option_setting_dualsel))
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__OPTION_SETTING_OFS_End = .;
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} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
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SECTION_PROLOGUE(.option_setting_sas,,)
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{
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__OPTION_SETTING_SAS_Start = .;
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KEEP(*(.option_setting_sas))
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__OPTION_SETTING_SAS_End = .;
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} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
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SECTION_PROLOGUE(.option_setting_s,,)
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{
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__OPTION_SETTING_S_Start = .;
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KEEP(*(.option_setting_ofs1_sec))
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. = __OPTION_SETTING_S_Start + 0x04;
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KEEP(*(.option_setting_ofs3_sec))
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. = __OPTION_SETTING_S_Start + 0x10;
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KEEP(*(.option_setting_banksel_sec))
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. = __OPTION_SETTING_S_Start + 0x40;
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KEEP(*(.option_setting_bps_sec0))
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. = __OPTION_SETTING_S_Start + 0x44;
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KEEP(*(.option_setting_bps_sec1))
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. = __OPTION_SETTING_S_Start + 0x48;
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KEEP(*(.option_setting_bps_sec2))
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. = __OPTION_SETTING_S_Start + 0x4C;
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KEEP(*(.option_setting_bps_sec3))
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. = __OPTION_SETTING_S_Start + 0x60;
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KEEP(*(.option_setting_pbps_sec0))
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. = __OPTION_SETTING_S_Start + 0x64;
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KEEP(*(.option_setting_pbps_sec1))
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. = __OPTION_SETTING_S_Start + 0x68;
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KEEP(*(.option_setting_pbps_sec2))
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. = __OPTION_SETTING_S_Start + 0x6C;
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KEEP(*(.option_setting_pbps_sec3))
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. = __OPTION_SETTING_S_Start + 0x80;
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KEEP(*(.option_setting_ofs1_sel))
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. = __OPTION_SETTING_S_Start + 0x84;
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KEEP(*(.option_setting_ofs3_sel))
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. = __OPTION_SETTING_S_Start + 0x90;
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KEEP(*(.option_setting_banksel_sel))
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. = __OPTION_SETTING_S_Start + 0xC0;
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KEEP(*(.option_setting_bps_sel0))
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. = __OPTION_SETTING_S_Start + 0xC4;
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KEEP(*(.option_setting_bps_sel1))
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. = __OPTION_SETTING_S_Start + 0xC8;
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KEEP(*(.option_setting_bps_sel2))
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. = __OPTION_SETTING_S_Start + 0xCC;
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KEEP(*(.option_setting_bps_sel3))
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__OPTION_SETTING_S_End = .;
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} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF

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