xtensa: fix numerous checkpatch issues

Change-Id: I903f5f0692849fb9e7bf5d978b63b12bf1bd6e33
Signed-off-by: Andrew Boie <[email protected]>

Author: Andrew Boie

arch/xtensa/core/atomic.S

@@ -92,9 +92,9 @@ atomic_get:
  * @brief Atomically increment a memory location
  *
  * This routine atomically increments the value in <target>.  The operation is
- * done using unsigned integer arithmetic.  Various CPU architectures may impose
- * restrictions with regards to the alignment and cache attributes of the
- * atomic_t type.
+ * done using unsigned integer arithmetic.  Various CPU architectures may
+ * impose restrictions with regards to the alignment and cache attributes of
+ * the atomic_t type.
  *
  * This routine can be used from both task and interrupt level.
  *
@@ -126,9 +126,9 @@ atomic_inc:
  * @brief Atomically add a value to a memory location
  *
  * This routine atomically adds the contents of <target> and <value>, placing
- * the result in <target>. The operation is done using signed integer arithmetic.
- * Various CPU architectures may impose restrictions with regards to the
- * alignment and cache attributes of the atomic_t type.
+ * the result in <target>. The operation is done using signed integer
+ * arithmetic.  Various CPU architectures may impose restrictions with regards
+ * to the alignment and cache attributes of the atomic_t type.
  *
  * This routine can be used from both task and interrupt level.
  *
@@ -369,10 +369,10 @@ atomic_xor:
  *
  * @brief Atomically compare-and-swap the contents of a memory location
  *
- * This routine performs an atomic compare-and-swap. testing that the contents of
- * <target> contains <oldValue>, and if it does, setting the value of <target>
- * to <newValue>. Various CPU architectures may impose restrictions with regards
- * to the alignment and cache attributes of the atomic_t type.
+ * This routine performs an atomic compare-and-swap. testing that the contents
+ * of <target> contains <oldValue>, and if it does, setting the value of
+ * <target> to <newValue>. Various CPU architectures may impose restrictions
+ * with regards to the alignment and cache attributes of the atomic_t type.
  *
  * This routine can be used from both task and interrupt level.
  *

arch/xtensa/core/crt1-boards.S

@@ -79,7 +79,9 @@ _start:
 	 * It is also the return address, where zero indicates
 	 * that the frame used by _start is the bottommost frame.
 	 */
-#if !XCHAL_HAVE_HALT || !XCHAL_HAVE_BOOTLOADER		 /* not needed for Xtensa TX */
+
+/* not needed for Xtensa TX */
+#if !XCHAL_HAVE_HALT || !XCHAL_HAVE_BOOTLOADER
 	movi	a0, 0		 /* keep this register zero. */
 #endif
 
@@ -91,22 +93,25 @@ _start:
 	 * Initialize the stack pointer.
 	 * See the "ABI and Software Conventions" chapter in the
 	 * Xtensa ISA Reference manual for details.
-
+	 *
 	 * NOTE: Because the _start routine does not use any memory in its
 	 * stack frame, and because all of its CALL instructions use a
 	 * window size of 4 (or zero), the stack frame for _start can be empty.
 	 */
 	movi	sp, __stack
 
 	/*
-	 *  Now that sp (a1) is set, we can set PS as per the application
-	 *  (user vector mode, enable interrupts, enable window exceptions if applicable).
+	 *  Now that sp (a1) is set, we can set PS as per the application (user
+	 *  vector mode, enable interrupts, enable window exceptions if
+	 *  applicable).
 	 */
 #if XCHAL_HAVE_EXCEPTIONS
 # ifdef __XTENSA_CALL0_ABI__
-	movi	a3, PS_UM		/* PS.WOE = 0, PS.UM = 1, PS.EXCM = 0, PS.INTLEVEL = 0 */
+	/* PS.WOE = 0, PS.UM = 1, PS.EXCM = 0, PS.INTLEVEL = 0 */
+	movi	a3, PS_UM
 # else
-	movi	a3, PS_UM|PS_WOE	/* PS.WOE = 1, PS.UM = 1, PS.EXCM = 0, PS.INTLEVEL = 0 */
+	/* PS.WOE = 1, PS.UM = 1, PS.EXCM = 0, PS.INTLEVEL = 0 */
+	movi	a3, PS_UM|PS_WOE
 # endif
 	wsr	a3, PS
 	rsync
@@ -168,13 +173,13 @@ _start:
 	addi   	a6, a6, 8	/* next entry */
 	sub	a10, a9, a8	/* a10 = length, assumed a multiple of 4 */
 	bbci.l	a10, 2, .L1zte
-	s32i	a0, a8, 0	/* clear 4 bytes to make length multiple of 8 */
+	s32i	a0, a8, 0	/* clear 4 bytes to make len multiple of 8 */
 	addi	a8, a8, 4
 .L1zte:	bbci.l	a10, 3, .L2zte
-	s32i	a0, a8, 0	/* clear 8 bytes to make length multiple of 16 */
+	s32i	a0, a8, 0	/* clear 8 bytes to make len multiple of 16 */
 	s32i	a0, a8, 4
 	addi	a8, a8, 8
-.L2zte:	srli	a10, a10, 4	/* length is now multiple of 16, divide by 16 */
+.L2zte:	srli	a10, a10, 4	/* len is now multiple of 16, divide by 16 */
 	floopnez	a10, clearzte
 	s32i	a0, a8,	 0	/* clear 16 bytes at a time... */
 	s32i	a0, a8,	 4
@@ -189,18 +194,19 @@ _start:
 
 
 	/*
-	 * We can now call C code, the C calling environment has been initialized.
+	 * We can now call C code, the C calling environment has been
+	 * initialized.
 	 *
-	 *  From this point on, we use ABI-specific macros to refer to registers a0 .. a15
-	 *  (ARG#).
+	 * From this point on, we use ABI-specific macros to refer to
+	 * registers a0 .. a15 (ARG#).
 	 */
 
 #if XCHAL_HAVE_HALT
 
 	/*
 	 * Assume minimalist environment for memory-constrained TX cores.
-	 *  No C library or board initialization, no parameters passed to main
-	 *  (assume declared as "void main(void)") and no call to exit().
+	 * No C library or board initialization, no parameters passed to main
+	 * (assume declared as "void main(void)") and no call to exit().
 	 */
 	CALL	main
 	halt
@@ -220,10 +226,8 @@ _start:
 	 *
 	 *  void __clibrary_init(int argc, char ** argv, char ** environ,
 	 *		void(*init_func)(void), void(*fini_func)(void));
+	 *  Pass an empty argv array, with an empty string as the program name
 	 */
-
-	 *  Pass an empty argv array, with an empty string as the program name. */
-
 	movi	ARG1, _start_argc	/* argc address */
 	movi	ARG2, _start_argv	/* argv = ["", 0] */
 	movi	ARG3, _start_envp	/* envp = [0] */
@@ -238,7 +242,9 @@ _start:
 	movi	ARG3, _start_envp	/* envp = [0] */
 	l32i	ARG1, ARG1, 0		/* argc = 1 */
 	CALL	main
-	/*  The return value is the same register as the first outgoing argument. */
+	/* The return value is the same register as the first
+	 * outgoing argument.
+	 */
 	CALL	exit			/* exit with main's return value */
 	/* Does not return here. */
 
@@ -253,7 +259,8 @@ _start_argv:
 	.word	_start_null	/* empty program name */
 _start_null:
 _start_envp:
-	.word	0		/* end of argv array, empty string, empty environ */
+	/* end of argv array, empty string, empty environ */
+	.word	0
 _start_argc:
 	.word	1		/* one argument (program name) */
 	.text

arch/xtensa/core/crt1-sim.S

@@ -111,12 +111,12 @@ __start:
 	simcall	/* returns size of argv[] + its strings in a2 */
 #if XCHAL_HAVE_PIF
 	/*
-	 * The stack only needs 16-byte alignment.
-	 * However, here we round up the argv size further to 128 byte multiples
-	 * so that in most cases, variations in argv[0]'s path do not result in
-	 * different stack allocation.  Otherwise, such variations can impact
-	 * execution timing (eg. due to cache effects etc) for the same code and data.
-	 * If we have a PIF, it's more likely the extra required space is okay.
+	 * The stack only needs 16-byte alignment.  However, here we round up
+	 * the argv size further to 128 byte multiples so that in most cases,
+	 * variations in argv[0]'s path do not result in different stack
+	 * allocation.  Otherwise, such variations can impact execution timing
+	 * (eg. due to cache effects etc) for the same code and data.  If we
+	 * have a PIF, it's more likely the extra required space is okay.
 	 */
 	addi	a2, a2, 127
 	srli	a2, a2, 7
@@ -139,14 +139,17 @@ __start:
 
 
 	/*
-	 *  Now that sp (a1) is set, we can set PS as per the application
-	 *  (user vector mode, enable interrupts, enable window exceptions if applicable).
+	 *  Now that sp (a1) is set, we can set PS as per the application (user
+	 *  vector mode, enable interrupts, enable window exceptions if
+	 *  applicable).
 	 */
 #if XCHAL_HAVE_EXCEPTIONS
 # ifdef __XTENSA_CALL0_ABI__
-	movi	a3, PS_UM /* PS.WOE = 0, PS.UM = 1, PS.EXCM = 0, PS.INTLEVEL = 0 */
+	/* PS.WOE = 0, PS.UM = 1, PS.EXCM = 0, PS.INTLEVEL = 0 */
+	movi	a3, PS_UM
 # else
-	movi	a3, PS_UM|PS_WOE /* PS.WOE = 1, PS.UM = 1, PS.EXCM = 0, PS.INTLEVEL = 0 */
+	/* PS.WOE = 1, PS.UM = 1, PS.EXCM = 0, PS.INTLEVEL = 0 */
+	movi	a3, PS_UM|PS_WOE
 # endif
 	wsr	a3, PS
 	rsync
@@ -180,9 +183,11 @@ __start:
 	CALLX	a4
 1:
 
-
 	/*  The new ISS simcall only appeared after RB-2007.2:  */
-#if !XCHAL_HAVE_BOOTLOADER && (XCHAL_HW_MAX_VERSION > XTENSA_HWVERSION_RB_2007_2)	/* pre-LX2 cores only */
+
+#if !XCHAL_HAVE_BOOTLOADER && \
+	(XCHAL_HW_MAX_VERSION > XTENSA_HWVERSION_RB_2007_2)
+	/* pre-LX2 cores only */
 	/*
 	 *  Clear the BSS (uninitialized data) segments.
 	 *  This code supports multiple zeroed sections (*.bss).
@@ -223,7 +228,9 @@ __start:
 
 	/*  Call:   int _Cstart(); */
 	CALL	_Cstart
-	/*  The return value is the same register as the first outgoing argument. */
+	/* The return value is the same register as the first outgoing
+	 * argument.
+	 */
 	CALL	exit
 	/* Does not return here. */
 

arch/xtensa/core/irq_manage.c

@@ -15,14 +15,14 @@
  *
  * The priority is verified if ASSERT_ON is enabled.
  *
- * The priority is verified if ASSERT_ON is enabled. The maximum number
- * of priority levels is a little complex, as there are some hardware
- * priority levels which are reserved: three for various types of exceptions,
- * and possibly one additional to support zero latency interrupts.
+ * The priority is verified if ASSERT_ON is enabled. The maximum number of
+ * priority levels is a little complex, as there are some hardware priority
+ * levels which are reserved: three for various types of exceptions, and
+ * possibly one additional to support zero latency interrupts.
  *
  * Valid values are from 1 to 6. Interrupts of priority 1 are not masked when
- * interrupts are locked system-wide, so care must be taken when using them. ISR
- * installed with priority 0 interrupts cannot make kernel calls.
+ * interrupts are locked system-wide, so care must be taken when using them.
+ * ISR installed with priority 0 interrupts cannot make kernel calls.
  *
  * @return N/A
  */
@@ -32,5 +32,7 @@ void _irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
 	__ASSERT(prio < XCHAL_EXCM_LEVEL + 1,
 		 "invalid priority %d! values must be less than %d\n",
 		 prio, XCHAL_EXCM_LEVEL + 1);
-	/* TODO: Write code to set priority if this is ever possible on Xtensa */
+	/* TODO: Write code to set priority if this is ever possible on
+	 * Xtensa
+	 */
 }

arch/xtensa/core/irq_offload.c

@@ -12,9 +12,6 @@
  * Xtensa core should support software interrupt in order to allow using
  * irq_offload feature
  */
-#ifndef CONFIG_IRQ_OFFLOAD_INTNUM
-#error "Please add entry for IRQ_OFFLOAD_INTNUM option to your arch/xtensa/soc/${XTENSA_CORE}/Kconfig file in order to use IRQ offload on this core."
-#endif
 
 static irq_offload_routine_t offload_routine;
 static void *offload_param;