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michal-smolanashif
michal-smola
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dts: mcxc: Add initial support for NXP MCXC socs
Add initial support for NXP MCXC socs. Signed-off-by: Michal Smola <[email protected]>
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‎dts/arm/nxp/nxp_mcxc141.dtsi‎

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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <nxp/nxp_mcxc_common.dtsi>
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&sram0 {
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reg = <0x1FFFF000 DT_SIZE_K(8)>;
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};
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&flash0 {
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reg = <0 DT_SIZE_K(32)>;
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};

‎dts/arm/nxp/nxp_mcxc142.dtsi‎

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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <nxp/nxp_mcxc_common.dtsi>
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&sram0 {
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reg = <0x1FFFF000 DT_SIZE_K(16)>;
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};
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&flash0 {
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reg = <0 DT_SIZE_K(64)>;
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};

‎dts/arm/nxp/nxp_mcxc242.dtsi‎

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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <nxp/nxp_mcxc_common.dtsi>
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&sram0 {
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reg = <0x1FFFF000 DT_SIZE_K(16)>;
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};
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&flash0 {
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reg = <0 DT_SIZE_K(64)>;
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};

‎dts/arm/nxp/nxp_mcxc_common.dtsi‎

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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <arm/armv6-m.dtsi>
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#include <zephyr/dt-bindings/adc/adc.h>
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#include <zephyr/dt-bindings/clock/kinetis_sim.h>
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#include <zephyr/dt-bindings/clock/kinetis_mcg.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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/ {
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chosen {
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zephyr,flash-controller = &ftfa;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m0+";
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reg = <0>;
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};
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};
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sram0: memory@1FFFF000 {
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compatible = "mmio-sram";
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};
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/* Dummy pinctrl node, filled with pin mux options at board level */
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pinctrl: pinctrl {
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compatible = "nxp,kinetis-pinctrl";
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status = "okay";
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};
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clocks {
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osc: osc {
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compatible = "nxp,mcxc-osc";
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#clock-cells = <0>;
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load-capacitance-picofarads = <0>;
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mode = "external";
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};
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};
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soc {
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ftfa: flash-controller@40020000 {
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compatible = "nxp,kinetis-ftfa";
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reg = <0x40020000 0x14>;
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interrupts = <5 0>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <1>;
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fsec = <0xff>;
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fopt = <0xff>;
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config-field-offset = <0x400>;
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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erase-block-size = <1024>;
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write-block-size = <4>;
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};
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};
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mcg: clock-controller@40064000 {
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compatible = "nxp,kinetis-mcg";
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reg = <0x40064000 0xd>;
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fcrdiv = <0>;
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lircdiv2 = <0>;
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#clock-cells = <1>;
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};
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sim: sim@40047000 {
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compatible = "nxp,kinetis-sim";
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reg = <0x40047000 0x1060>;
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#clock-cells = <3>;
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core_clk {
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compatible = "fixed-factor-clock";
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clocks = <&mcg KINETIS_MCG_OUT_CLK>;
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clock-div = <1>;
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#clock-cells = <0>;
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};
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flash_clk {
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compatible = "fixed-factor-clock";
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clocks = <&mcg KINETIS_MCG_OUT_CLK>;
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clock-div = <2>;
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#clock-cells = <0>;
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};
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};
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porta: pinmux@40049000 {
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compatible = "nxp,kinetis-pinmux";
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reg = <0x40049000 0xd0>;
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clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>;
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};
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portb: pinmux@4004a000 {
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compatible = "nxp,kinetis-pinmux";
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reg = <0x4004a000 0xd0>;
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clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>;
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};
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portc: pinmux@4004b000 {
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compatible = "nxp,kinetis-pinmux";
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reg = <0x4004b000 0xd0>;
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clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>;
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};
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portd: pinmux@4004c000 {
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compatible = "nxp,kinetis-pinmux";
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reg = <0x4004c000 0xd0>;
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clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 12>;
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};
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porte: pinmux@4004d000 {
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compatible = "nxp,kinetis-pinmux";
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reg = <0x4004d000 0xd0>;
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clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 13>;
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};
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gpioa: gpio@400ff000 {
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compatible = "nxp,kinetis-gpio";
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status = "disabled";
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reg = <0x400ff000 0x40>;
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interrupts = <30 2>;
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&porta>;
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};
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gpiob: gpio@400ff040 {
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compatible = "nxp,kinetis-gpio";
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status = "disabled";
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reg = <0x400ff040 0x40>;
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&portb>;
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};
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gpioc: gpio@400ff080 {
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compatible = "nxp,kinetis-gpio";
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status = "disabled";
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reg = <0x400ff080 0x40>;
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interrupts = <31 2>;
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&portc>;
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};
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gpiod: gpio@400ff0c0 {
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compatible = "nxp,kinetis-gpio";
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status = "disabled";
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reg = <0x400ff0c0 0x40>;
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&portd>;
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};
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gpioe: gpio@400ff100 {
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compatible = "nxp,kinetis-gpio";
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status = "disabled";
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reg = <0x400ff100 0x40>;
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gpio-controller;
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#gpio-cells = <2>;
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nxp,kinetis-port = <&porte>;
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};
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adc0: adc@4003b000{
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compatible = "nxp,kinetis-adc16";
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reg = <0x4003b000 0x70>;
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interrupts = <15 0>;
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status = "disabled";
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#io-channel-cells = <1>;
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};
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i2c0: i2c@40066000 {
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compatible = "nxp,kinetis-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40066000 0x1000>;
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interrupts = <8 0>;
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clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 6>;
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status = "disabled";
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};
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i2c1: i2c@40067000 {
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compatible = "nxp,kinetis-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40067000 0x1000>;
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interrupts = <9 0>;
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clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 7>;
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status = "disabled";
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};
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lpuart0: uart@40054000 {
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compatible = "nxp,kinetis-lpuart";
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reg = <0x40054000 0x1000>;
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interrupts = <12 0>;
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clocks = <&sim KINETIS_SIM_MCGPCLK 0x1038 20>;
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status = "disabled";
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};
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lpuart1: uart@40055000 {
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compatible = "nxp,kinetis-lpuart";
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reg = <0x40055000 0x1000>;
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interrupts = <13 0>;
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clocks = <&sim KINETIS_SIM_MCGPCLK 0x1038 21>;
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status = "disabled";
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};
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uart2: uart@4006c000 {
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compatible = "nxp,kinetis-uart";
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reg = <0x4006c000 0x1000>;
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interrupts = <14 0>;
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interrupt-names = "status";
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clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 12>;
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status = "disabled";
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};
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tpm0: pwm@40038000 {
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compatible = "nxp,kinetis-tpm";
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reg = <0x40038000 0x88>;
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interrupts = <17 0>;
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clocks = <&sim KINETIS_SIM_MCGPCLK 0x103C 24>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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tpm1: pwm@40039000 {
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compatible = "nxp,kinetis-tpm";
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reg = <0x40039000 0x88>;
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interrupts = <18 0>;
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clocks = <&sim KINETIS_SIM_MCGPCLK 0x103C 25>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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tpm2: pwm@4003a000 {
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compatible = "nxp,kinetis-tpm";
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reg = <0x4003a000 0x88>;
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interrupts = <19 0>;
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clocks = <&sim KINETIS_SIM_MCGPCLK 0x103C 26>;
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status = "disabled";
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#pwm-cells = <3>;
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <2>;
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};

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