Skip to content

Commit 42cc35f

Browse files
danieldegrassemmahadevan108
danieldegrasse
authored and
mmahadevan108
committed
soc: nxp: consolidate nxp port pinctrl headers
NXP PORT IP instantiations often have different features absent, IE input buffer, open drain, or slew rate support. Check if the relevant PCR register bitmasks are defined in the common pin control file, and define the bitmasks to 0x0 (no effect) if they are not. This allows us to further consolidate the pinctrl_soc.h headers for SOCs using the PORT IP. Signed-off-by: Daniel DeGrasse <[email protected]>
1 parent a36c7dd commit 42cc35f

File tree

8 files changed

+34
-157
lines changed

8 files changed

+34
-157
lines changed

‎drivers/pinctrl/pinctrl_nxp_port.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@ static PORT_Type *ports[] = {
3232

3333
#define PIN(mux) (((mux) & 0xFC00000) >> 22)
3434
#define PORT(mux) (((mux) & 0xF0000000) >> 28)
35-
#define PINCFG(mux) ((mux) & Z_PINCTRL_KINETIS_PCR_MASK)
35+
#define PINCFG(mux) ((mux) & Z_PINCTRL_NXP_PORT_PCR_MASK)
3636

3737
struct pinctrl_mcux_config {
3838
const struct device *clock_dev;
@@ -47,7 +47,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
4747
uint8_t pin = PIN(pins[i]);
4848
uint16_t mux = PINCFG(pins[i]);
4949

50-
base->PCR[pin] = (base->PCR[pin] & (~Z_PINCTRL_KINETIS_PCR_MASK)) | mux;
50+
base->PCR[pin] = (base->PCR[pin] & (~Z_PINCTRL_NXP_PORT_PCR_MASK)) | mux;
5151
}
5252
return 0;
5353
}

‎include/zephyr/drivers/pinctrl/pinctrl_soc_kinetis_common.h‎ renamed to ‎include/zephyr/drivers/pinctrl/pinctrl_nxp_port_common.h‎

Lines changed: 25 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -6,50 +6,49 @@
66

77
/*
88
* @file
9-
* NXP Kinetis SOC specific helpers for pinctrl driver
9+
* NXP PORT SOC specific helpers for pinctrl driver
1010
*/
1111

1212

13-
#ifndef ZEPHYR_SOC_ARM_NXP_KINETIS_COMMON_PINCTRL_SOC_H_
14-
#define ZEPHYR_SOC_ARM_NXP_KINETIS_COMMON_PINCTRL_SOC_H_
13+
#ifndef ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_NXP_PORT_COMMON_H_
14+
#define ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_NXP_PORT_COMMON_H_
1515

1616
/** @cond INTERNAL_HIDDEN */
1717

1818
#include <zephyr/devicetree.h>
1919
#include <zephyr/types.h>
2020

21+
/* Include SOC headers, so we get definitions for PCR bitmasks */
22+
#include <soc.h>
23+
2124
#ifdef __cplusplus
2225
extern "C" {
2326
#endif
2427

25-
26-
typedef uint32_t pinctrl_soc_pin_t;
27-
28-
/* Kinetis KW/KL/KE series does not support open drain. Define macros to have no effect
29-
* Note: KW22 and KW24 do support open drain, rest of KW series does not
28+
/*
29+
* Some PORT IP instantiations lack certain features, include input buffers,
30+
* open drain, and slew rate. If masks aren't defined for these bitfields,
31+
* define them to have no effect
3032
*/
31-
/* clang-format off */
32-
#if (defined(CONFIG_SOC_SERIES_KINETIS_KWX) && \
33-
!(defined(CONFIG_SOC_MKW24D5) || defined(CONFIG_SOC_MKW22D5))) || \
34-
defined(CONFIG_SOC_SERIES_KINETIS_KL2X) || defined(CONFIG_SOC_SERIES_KINETIS_KE1XF) || \
35-
defined(CONFIG_SOC_SERIES_KE1XZ)
36-
#define PORT_PCR_ODE(x) 0x0
37-
#define PORT_PCR_ODE_MASK 0x0
33+
#ifndef PORT_PCR_IBE_MASK /* Input buffer enable */
34+
#define PORT_PCR_IBE_MASK 0x0
35+
#define PORT_PCR_IBE(x) 0x0
3836
#endif
39-
/* clang-format on */
4037

41-
/* Kinetis KE series does not support slew rate. Define macros to have no effect */
42-
#if defined(CONFIG_SOC_SERIES_KINETIS_KE1XF) || defined(CONFIG_SOC_SERIES_KE1XZ)
43-
#define PORT_PCR_SRE(x) 0x0
38+
#ifndef PORT_PCR_SRE_MASK /* Slew rate */
4439
#define PORT_PCR_SRE_MASK 0x0
40+
#define PORT_PCR_SRE(x) 0x0
4541
#endif
4642

47-
#if !(defined(CONFIG_SOC_SERIES_MCXA))
48-
#define PORT_PCR_IBE(x) 0x0
49-
#define PORT_PCR_IBE_MASK 0x0
43+
#ifndef PORT_PCR_ODE_MASK /* Open drain */
44+
#define PORT_PCR_ODE_MASK 0x0
45+
#define PORT_PCR_ODE(x) 0x0
5046
#endif
5147

52-
#define Z_PINCTRL_KINETIS_PINCFG(node_id) \
48+
49+
typedef uint32_t pinctrl_soc_pin_t;
50+
51+
#define Z_PINCTRL_NXP_PORT_PINCFG(node_id) \
5352
(PORT_PCR_DSE(DT_ENUM_IDX(node_id, drive_strength)) | \
5453
PORT_PCR_PS(DT_PROP(node_id, bias_pull_up)) | \
5554
PORT_PCR_PE(DT_PROP(node_id, bias_pull_up)) | \
@@ -59,12 +58,12 @@ typedef uint32_t pinctrl_soc_pin_t;
5958
PORT_PCR_IBE(DT_PROP(node_id, input_enable)) | \
6059
PORT_PCR_PFE(DT_PROP(node_id, nxp_passive_filter)))
6160

62-
#define Z_PINCTRL_KINETIS_PCR_MASK \
61+
#define Z_PINCTRL_NXP_PORT_PCR_MASK \
6362
(PORT_PCR_MUX_MASK | PORT_PCR_DSE_MASK | PORT_PCR_ODE_MASK | PORT_PCR_PFE_MASK | \
6463
PORT_PCR_IBE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK)
6564

6665
#define Z_PINCTRL_STATE_PIN_INIT(group, pin_prop, idx) \
67-
DT_PROP_BY_IDX(group, pin_prop, idx) | Z_PINCTRL_KINETIS_PINCFG(group),
66+
DT_PROP_BY_IDX(group, pin_prop, idx) | Z_PINCTRL_NXP_PORT_PINCFG(group),
6867

6968
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
7069
{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux, \
@@ -76,4 +75,4 @@ typedef uint32_t pinctrl_soc_pin_t;
7675

7776
/** @endcond */
7877

79-
#endif /* ZEPHYR_SOC_ARM_NXP_KINETIS_COMMON_PINCTRL_SOC_H_ */
78+
#endif /* ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_NXP_PORT_COMMON_H_ */

‎soc/nxp/kinetis/common/pinctrl_soc.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,4 +4,4 @@
44
* SPDX-License-Identifier: Apache-2.0
55
*/
66

7-
#include <zephyr/drivers/pinctrl/pinctrl_soc_kinetis_common.h>
7+
#include <zephyr/drivers/pinctrl/pinctrl_nxp_port_common.h>

‎soc/nxp/mcx/mcxa/pinctrl_soc.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,4 +4,4 @@
44
* SPDX-License-Identifier: Apache-2.0
55
*/
66

7-
#include <zephyr/drivers/pinctrl/pinctrl_soc_kinetis_common.h>
7+
#include <zephyr/drivers/pinctrl/pinctrl_nxp_port_common.h>

‎soc/nxp/mcx/mcxc/pinctrl_soc.h‎

Lines changed: 1 addition & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -4,46 +4,4 @@
44
* SPDX-License-Identifier: Apache-2.0
55
*/
66

7-
#ifndef ZEPHYR_SOC_ARM_NXP_MCXC_COMMON_PINCTRL_SOC_H_
8-
#define ZEPHYR_SOC_ARM_NXP_MCXC_COMMON_PINCTRL_SOC_H_
9-
10-
#include <zephyr/devicetree.h>
11-
#include <zephyr/types.h>
12-
13-
#ifdef __cplusplus
14-
extern "C" {
15-
#endif
16-
17-
typedef uint32_t pinctrl_soc_pin_t;
18-
19-
/* MCXC series does not support open drain. Define macros to have no effect */
20-
#define PORT_PCR_ODE(x) 0x0
21-
#define PORT_PCR_ODE_MASK 0x0
22-
23-
#define Z_PINCTRL_MCXC_PINCFG(node_id) \
24-
(PORT_PCR_DSE(DT_ENUM_IDX(node_id, drive_strength)) | \
25-
PORT_PCR_PS(DT_PROP(node_id, bias_pull_up)) | \
26-
PORT_PCR_PE(DT_PROP(node_id, bias_pull_up)) | \
27-
PORT_PCR_PE(DT_PROP(node_id, bias_pull_down)) | \
28-
PORT_PCR_ODE(DT_PROP(node_id, drive_open_drain)) | \
29-
PORT_PCR_SRE(DT_ENUM_IDX(node_id, slew_rate)) | \
30-
PORT_PCR_PFE(DT_PROP(node_id, nxp_passive_filter)))
31-
32-
#define Z_PINCTRL_KINETIS_PCR_MASK \
33-
(PORT_PCR_MUX_MASK | PORT_PCR_DSE_MASK | PORT_PCR_ODE_MASK | \
34-
PORT_PCR_PFE_MASK | PORT_PCR_SRE_MASK | PORT_PCR_PE_MASK | \
35-
PORT_PCR_PS_MASK)
36-
37-
38-
#define Z_PINCTRL_STATE_PIN_INIT(group, pin_prop, idx) \
39-
DT_PROP_BY_IDX(group, pin_prop, idx) | Z_PINCTRL_MCXC_PINCFG(group),
40-
41-
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
42-
{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
43-
DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_STATE_PIN_INIT)};
44-
45-
#ifdef __cplusplus
46-
}
47-
#endif
48-
49-
#endif /* ZEPHYR_SOC_ARM_NXP_MCXC_COMMON_PINCTRL_SOC_H_ */
7+
#include <zephyr/drivers/pinctrl/pinctrl_nxp_port_common.h>

‎soc/nxp/mcx/mcxn/pinctrl_soc.h‎

Lines changed: 1 addition & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -4,43 +4,4 @@
44
* SPDX-License-Identifier: Apache-2.0
55
*/
66

7-
#ifndef ZEPHYR_SOC_ARM_NXP_MCX_COMMON_PINCTRL_SOC_H_
8-
#define ZEPHYR_SOC_ARM_NXP_MCX_COMMON_PINCTRL_SOC_H_
9-
10-
#include <zephyr/devicetree.h>
11-
#include <zephyr/types.h>
12-
13-
#ifdef __cplusplus
14-
extern "C" {
15-
#endif
16-
17-
typedef uint32_t pinctrl_soc_pin_t;
18-
19-
#define Z_PINCTRL_MCX_PINCFG(node_id) \
20-
(PORT_PCR_DSE(DT_ENUM_IDX(node_id, drive_strength)) | \
21-
PORT_PCR_PS(DT_PROP(node_id, bias_pull_up)) | \
22-
PORT_PCR_PE(DT_PROP(node_id, bias_pull_up)) | \
23-
PORT_PCR_PE(DT_PROP(node_id, bias_pull_down)) | \
24-
PORT_PCR_ODE(DT_PROP(node_id, drive_open_drain)) | \
25-
PORT_PCR_SRE(DT_ENUM_IDX(node_id, slew_rate)) | \
26-
PORT_PCR_IBE(DT_PROP(node_id, input_enable)) | \
27-
PORT_PCR_PFE(DT_PROP(node_id, nxp_passive_filter)))
28-
29-
#define Z_PINCTRL_KINETIS_PCR_MASK \
30-
(PORT_PCR_IBE_MASK | PORT_PCR_MUX_MASK | PORT_PCR_DSE_MASK | \
31-
PORT_PCR_ODE_MASK | PORT_PCR_PFE_MASK | PORT_PCR_SRE_MASK | \
32-
PORT_PCR_PE_MASK | PORT_PCR_PS_MASK)
33-
34-
35-
#define Z_PINCTRL_STATE_PIN_INIT(group, pin_prop, idx) \
36-
DT_PROP_BY_IDX(group, pin_prop, idx) | Z_PINCTRL_MCX_PINCFG(group),
37-
38-
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
39-
{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
40-
DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_STATE_PIN_INIT)};
41-
42-
#ifdef __cplusplus
43-
}
44-
#endif
45-
46-
#endif /* ZEPHYR_SOC_ARM_NXP_MCX_COMMON_PINCTRL_SOC_H_ */
7+
#include <zephyr/drivers/pinctrl/pinctrl_nxp_port_common.h>

‎soc/nxp/mcx/mcxw/pinctrl_soc.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,4 +4,4 @@
44
* SPDX-License-Identifier: Apache-2.0
55
*/
66

7-
#include <zephyr/drivers/pinctrl/pinctrl_soc_kinetis_common.h>
7+
#include <zephyr/drivers/pinctrl/pinctrl_nxp_port_common.h>

‎soc/nxp/s32/s32k1/pinctrl_soc.h‎

Lines changed: 2 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -1,48 +1,7 @@
11
/*
2-
* Copyright 2023 NXP
2+
* Copyright 2023-2024 NXP
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
66

7-
/*
8-
* @file
9-
* NXP S32K1 SOC specific helpers for pinctrl driver
10-
*/
11-
12-
#ifndef ZEPHYR_SOC_ARM_NXP_S32_S32K1_PINCTRL_SOC_H_
13-
#define ZEPHYR_SOC_ARM_NXP_S32_S32K1_PINCTRL_SOC_H_
14-
15-
#include <zephyr/devicetree.h>
16-
#include <zephyr/types.h>
17-
18-
#ifdef __cplusplus
19-
extern "C" {
20-
#endif
21-
22-
/** @cond INTERNAL_HIDDEN */
23-
24-
typedef uint32_t pinctrl_soc_pin_t;
25-
26-
#define Z_PINCTRL_KINETIS_PINCFG(node_id) \
27-
(PORT_PCR_DSE(DT_ENUM_IDX(node_id, drive_strength)) | \
28-
PORT_PCR_PS(DT_PROP(node_id, bias_pull_up)) | \
29-
PORT_PCR_PE(DT_PROP(node_id, bias_pull_up)) | \
30-
PORT_PCR_PE(DT_PROP(node_id, bias_pull_down)) | \
31-
PORT_PCR_PFE(DT_PROP(node_id, nxp_passive_filter)))
32-
33-
#define Z_PINCTRL_KINETIS_PCR_MASK \
34-
(PORT_PCR_MUX_MASK | PORT_PCR_DSE_MASK | PORT_PCR_PFE_MASK | \
35-
PORT_PCR_PE_MASK | PORT_PCR_PS_MASK)
36-
37-
#define Z_PINCTRL_STATE_PIN_INIT(group, pin_prop, idx) \
38-
DT_PROP_BY_IDX(group, pin_prop, idx) | Z_PINCTRL_KINETIS_PINCFG(group),
39-
40-
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
41-
{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
42-
DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_STATE_PIN_INIT)};
43-
44-
#ifdef __cplusplus
45-
}
46-
#endif
47-
48-
#endif /* ZEPHYR_SOC_ARM_NXP_S32_S32K1_PINCTRL_SOC_H_ */
7+
#include <zephyr/drivers/pinctrl/pinctrl_nxp_port_common.h>

0 commit comments

Comments
 (0)