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tmon-nordicfabiobaltieri
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drivers: udc_dwc2: Add power saving related registers
Add Power and clock gating control register to register map and appropriate bit macros. Add missing GHWCFG4, GLPMCFG and GPWRDN bits. Signed-off-by: Tomasz Moń <[email protected]>
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‎drivers/usb/common/usb_dwc2_hw.h‎

Lines changed: 184 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -110,13 +110,12 @@ struct usb_dwc2_reg {
110110
volatile uint32_t reserved5[16];
111111
struct usb_dwc2_in_ep in_ep[16];
112112
struct usb_dwc2_out_ep out_ep[16];
113+
volatile uint32_t reserved6[64];
114+
volatile uint32_t pcgcctl;
113115
};
114116

115-
/*
116-
* With the maximum number of supported endpoints, register map
117-
* of the controller must be equal to 0x0D00.
118-
*/
119-
BUILD_ASSERT(sizeof(struct usb_dwc2_reg) == 0x0D00);
117+
/* The last register (PCGCCTL) must be at offset 0xE00. */
118+
BUILD_ASSERT(offsetof(struct usb_dwc2_reg, pcgcctl) == 0x0E00);
120119

121120
/*
122121
* GET_FIELD/SET_FIELD macros below are intended to be used to define functions
@@ -430,14 +429,46 @@ USB_DWC2_GET_FIELD_DEFINE(ghwcfg3_xfersizewidth, GHWCFG3_XFERSIZEWIDTH)
430429

431430
/* GHWCFG4 register */
432431
#define USB_DWC2_GHWCFG4 0x0050UL
432+
#define USB_DWC2_GHWCFG4_DESCDMA_POS 31UL
433+
#define USB_DWC2_GHWCFG4_DESCDMA BIT(USB_DWC2_GHWCFG4_DESCDMA_POS)
434+
#define USB_DWC2_GHWCFG4_DESCDMAENABLED_POS 30UL
435+
#define USB_DWC2_GHWCFG4_DESCDMAENABLED BIT(USB_DWC2_GHWCFG4_DESCDMAENABLED_POS)
433436
#define USB_DWC2_GHWCFG4_INEPS_POS 26UL
434437
#define USB_DWC2_GHWCFG4_INEPS_MASK (0xFUL << USB_DWC2_GHWCFG4_INEPS_POS)
435438
#define USB_DWC2_GHWCFG4_DEDFIFOMODE_POS 25UL
436439
#define USB_DWC2_GHWCFG4_DEDFIFOMODE BIT(USB_DWC2_GHWCFG4_DEDFIFOMODE_POS)
440+
#define USB_DWC2_GHWCFG4_SESSENDFLTR_POS 24UL
441+
#define USB_DWC2_GHWCFG4_SESSENDFLTR BIT(USB_DWC2_GHWCFG4_SESSENDFLTR_POS)
442+
#define USB_DWC2_GHWCFG4_BVALIDFLTR_POS 23UL
443+
#define USB_DWC2_GHWCFG4_BVALIDFLTR BIT(USB_DWC2_GHWCFG4_BVALIDFLTR_POS)
444+
#define USB_DWC2_GHWCFG4_AVALIDFLTR_POS 22UL
445+
#define USB_DWC2_GHWCFG4_AVALIDFLTR BIT(USB_DWC2_GHWCFG4_AVALIDFLTR_POS)
446+
#define USB_DWC2_GHWCFG4_VBUSVALIDFLTR_POS 21UL
447+
#define USB_DWC2_GHWCFG4_VBUSVALIDFLTR BIT(USB_DWC2_GHWCFG4_VBUSVALIDFLTR_POS)
448+
#define USB_DWC2_GHWCFG4_IDDGFLTR_POS 20UL
449+
#define USB_DWC2_GHWCFG4_IDDGFLTR BIT(USB_DWC2_GHWCFG4_IDDGFLTR_POS)
437450
#define USB_DWC2_GHWCFG4_NUMCTLEPS_POS 16UL
438451
#define USB_DWC2_GHWCFG4_NUMCTLEPS_MASK (0xFUL << USB_DWC2_GHWCFG4_NUMCTLEPS_POS)
439452
#define USB_DWC2_GHWCFG4_PHYDATAWIDTH_POS 14UL
440453
#define USB_DWC2_GHWCFG4_PHYDATAWIDTH_MASK (0x3UL << USB_DWC2_GHWCFG4_PHYDATAWIDTH_POS)
454+
#define USB_DWC2_GHWCFG4_ENHANCEDLPMSUPT_POS 13UL
455+
#define USB_DWC2_GHWCFG4_ENHANCEDLPMSUPT BIT(USB_DWC2_GHWCFG4_ENHANCEDLPMSUPT_POS)
456+
#define USB_DWC2_GHWCFG4_ACGSUPT_POS 12UL
457+
#define USB_DWC2_GHWCFG4_ACGSUPT BIT(USB_DWC2_GHWCFG4_ACGSUPT_POS)
458+
#define USB_DWC2_GHWCFG4_IPGISOCSUPT_POS 11UL
459+
#define USB_DWC2_GHWCFG4_IPGISOCSUPT BIT(USB_DWC2_GHWCFG4_IPGISOCSUPT_POS)
460+
#define USB_DWC2_GHWCFG4_SERVINTFLOW_POS 10UL
461+
#define USB_DWC2_GHWCFG4_SERVINTFLOW BIT(USB_DWC2_GHWCFG4_SERVINTFLOW_POS)
462+
#define USB_DWC2_GHWCFG4_ENHANCEDLPMSUPT1_POS 9UL
463+
#define USB_DWC2_GHWCFG4_ENHANCEDLPMSUPT1 BIT(USB_DWC2_GHWCFG4_ENHANCEDLPMSUPT1_POS)
464+
#define USB_DWC2_GHWCFG4_EXT_HIBERNATION_POS 7UL
465+
#define USB_DWC2_GHWCFG4_EXT_HIBERNATION BIT(USB_DWC2_GHWCFG4_EXT_HIBERNATION_POS)
466+
#define USB_DWC2_GHWCFG4_HIBERNATION_POS 6UL
467+
#define USB_DWC2_GHWCFG4_HIBERNATION BIT(USB_DWC2_GHWCFG4_HIBERNATION_POS)
468+
#define USB_DWC2_GHWCFG4_AHBFREQ_POS 5UL
469+
#define USB_DWC2_GHWCFG4_AHBFREQ BIT(USB_DWC2_GHWCFG4_AHBFREQ_POS)
470+
#define USB_DWC2_GHWCFG4_PARTIALPWRDN_POS 4UL
471+
#define USB_DWC2_GHWCFG4_PARTIALPWRDN BIT(USB_DWC2_GHWCFG4_PARTIALPWRDN_POS)
441472
#define USB_DWC2_GHWCFG4_NUMDEVPERIOEPS_POS 0UL
442473
#define USB_DWC2_GHWCFG4_NUMDEVPERIOEPS_MASK (0xFUL << USB_DWC2_GHWCFG4_NUMDEVPERIOEPS_POS)
443474

@@ -446,6 +477,130 @@ USB_DWC2_GET_FIELD_DEFINE(ghwcfg4_numctleps, GHWCFG4_NUMCTLEPS)
446477
USB_DWC2_GET_FIELD_DEFINE(ghwcfg4_phydatawidth, GHWCFG4_PHYDATAWIDTH)
447478
USB_DWC2_GET_FIELD_DEFINE(ghwcfg4_numdevperioeps, GHWCFG4_NUMDEVPERIOEPS)
448479

480+
/* LPM Config Register */
481+
#define USB_DWC2_GLPMCFG 0x0054UL
482+
#define USB_DWC2_GLPMCFG_LPM_RESTORESLPSTS_POS 29UL
483+
#define USB_DWC2_GLPMCFG_LPM_RESTORESLPSTS BIT(USB_DWC2_GLPMCFG_LPM_RESTORESLPSTS_POS)
484+
#define USB_DWC2_GLPMCFG_LPM_ENBESL_POS 28UL
485+
#define USB_DWC2_GLPMCFG_LPM_ENBESL BIT(USB_DWC2_GLPMCFG_LPM_ENBESL_POS)
486+
#define USB_DWC2_GLPMCFG_LPM_RETRYCNT_STS_POS 25UL
487+
#define USB_DWC2_GLPMCFG_LPM_RETRYCNT_STS_MASK (0x7UL << USB_DWC2_GLPMCFG_LPM_RETRYCNT_STS_POS)
488+
#define USB_DWC2_GLPMCFG_SNDLPM_POS 24UL
489+
#define USB_DWC2_GLPMCFG_SNDLPM BIT(USB_DWC2_GLPMCFG_SNDLPM_POS)
490+
/* Host mode LPM Retry Count and LPM Channel Index */
491+
#define USB_DWC2_GLPMCFG_LPM_RETRY_CNT_POS 21UL
492+
#define USB_DWC2_GLPMCFG_LPM_RETRY_CNT_MASK (0x7UL << USB_DWC2_GLPMCFG_LPM_RETRY_CNT_POS)
493+
#define USB_DWC2_GLPMCFG_LPM_CHNL_INDX_POS 17UL
494+
#define USB_DWC2_GLPMCFG_LPM_CHNL_INDX_MASK (0xFUL << USB_DWC2_GLPMCFG_LPM_CHNL_INDX_POS)
495+
/* Device mode LPM Accept Control */
496+
#define USB_DWC2_GLPMCFG_LPM_ACK_BULK_POS 23UL
497+
#define USB_DWC2_GLPMCFG_LPM_ACK_BULK BIT(USB_DWC2_GLPMCFG_LPM_ACK_BULK_POS)
498+
#define USB_DWC2_GLPMCFG_LPM_ACK_ISO_POS 22UL
499+
#define USB_DWC2_GLPMCFG_LPM_ACK_ISO BIT(USB_DWC2_GLPMCFG_LPM_ACK_ISO_POS)
500+
#define USB_DWC2_GLPMCFG_LPM_NYET_CTRL_POS 21UL
501+
#define USB_DWC2_GLPMCFG_LPM_NYET_CTRL BIT(USB_DWC2_GLPMCFG_LPM_NYET_CTRL_POS)
502+
#define USB_DWC2_GLPMCFG_LPM_ACK_INTR_POS 20UL
503+
#define USB_DWC2_GLPMCFG_LPM_ACK_INTR BIT(USB_DWC2_GLPMCFG_LPM_ACK_INTR_POS)
504+
#define USB_DWC2_GLPMCFG_L1RESUMEOK_POS 16UL
505+
#define USB_DWC2_GLPMCFG_L1RESUMEOK BIT(USB_DWC2_GLPMCFG_L1RESUMEOK_POS)
506+
#define USB_DWC2_GLPMCFG_SLPSTS_POS 15UL
507+
#define USB_DWC2_GLPMCFG_SLPSTS BIT(USB_DWC2_GLPMCFG_SLPSTS_POS)
508+
#define USB_DWC2_GLPMCFG_COREL1RES_POS 13UL
509+
#define USB_DWC2_GLPMCFG_COREL1RES_MASK (0x3UL << USB_DWC2_GLPMCFG_COREL1RES_POS)
510+
#define USB_DWC2_GLPMCFG_COREL1RES_ERROR 0
511+
#define USB_DWC2_GLPMCFG_COREL1RES_STALL 1
512+
#define USB_DWC2_GLPMCFG_COREL1RES_NYET 2
513+
#define USB_DWC2_GLPMCFG_COREL1RES_ACK 3
514+
#define USB_DWC2_GLPMCFG_HIRD_THRES_POS 8UL
515+
#define USB_DWC2_GLPMCFG_HIRD_THRES_MASK (0x1FUL << USB_DWC2_GLPMCFG_HIRD_THRES_POS)
516+
#define USB_DWC2_GLPMCFG_ENBLSLPM_POS 7UL
517+
#define USB_DWC2_GLPMCFG_ENBLSLPM BIT(USB_DWC2_GLPMCFG_ENBLSLPM_POS)
518+
#define USB_DWC2_GLPMCFG_BREMOTEWAKE_POS 6UL
519+
#define USB_DWC2_GLPMCFG_BREMOTEWAKE BIT(USB_DWC2_GLPMCFG_BREMOTEWAKE_POS)
520+
#define USB_DWC2_GLPMCFG_HIRD_POS 2UL
521+
#define USB_DWC2_GLPMCFG_HIRD_MASK (0xFUL << USB_DWC2_GLPMCFG_HIRD_POS)
522+
#define USB_DWC2_GLPMCFG_APPL1RES_POS 1UL
523+
#define USB_DWC2_GLPMCFG_APPL1RES BIT(USB_DWC2_GLPMCFG_APPL1RES_POS)
524+
#define USB_DWC2_GLPMCFG_LPMCAP_POS 0UL
525+
#define USB_DWC2_GLPMCFG_LPMCAP BIT(USB_DWC2_GLPMCFG_LPMCAP_POS)
526+
527+
USB_DWC2_GET_FIELD_DEFINE(glpmcfg_lpm_retrycnt_sts, GLPMCFG_LPM_RETRYCNT_STS)
528+
USB_DWC2_GET_FIELD_DEFINE(glpmcfg_lpm_retry_cnt, GLPMCFG_LPM_RETRY_CNT)
529+
USB_DWC2_GET_FIELD_DEFINE(glpmcfg_lpm_chnl_indx, GLPMCFG_LPM_CHNL_INDX)
530+
USB_DWC2_GET_FIELD_DEFINE(glpmcfg_corel1res, GLPMCFG_COREL1RES)
531+
USB_DWC2_GET_FIELD_DEFINE(glpmcfg_hird_thres, GLPMCFG_HIRD_THRES)
532+
USB_DWC2_GET_FIELD_DEFINE(glpmcfg_hird, GLPMCFG_HIRD)
533+
USB_DWC2_SET_FIELD_DEFINE(glpmcfg_lpm_retry_cnt, GLPMCFG_LPM_RETRY_CNT)
534+
USB_DWC2_SET_FIELD_DEFINE(glpmcfg_lpm_chnl_indx, GLPMCFG_LPM_CHNL_INDX)
535+
USB_DWC2_SET_FIELD_DEFINE(glpmcfg_hird_thres, GLPMCFG_HIRD_THRES)
536+
USB_DWC2_SET_FIELD_DEFINE(glpmcfg_hird, GLPMCFG_HIRD)
537+
538+
/* Global Power Down Register */
539+
#define USB_DWC2_GPWRDN 0x0058UL
540+
#define USB_DWC2_GPWRDN_MULTVALIDBC_POS 24UL
541+
#define USB_DWC2_GPWRDN_MULTVALIDBC_MASK (0x1FUL << USB_DWC2_GPWRDN_MULTVALIDBC_POS)
542+
#define USB_DWC2_GPWRDN_MULTVALIDBC_RID_0 0
543+
#define USB_DWC2_GPWRDN_MULTVALIDBC_RID_C 1
544+
#define USB_DWC2_GPWRDN_MULTVALIDBC_RID_B 2
545+
#define USB_DWC2_GPWRDN_MULTVALIDBC_RID_A 4
546+
#define USB_DWC2_GPWRDN_MULTVALIDBC_RID_GND 8
547+
#define USB_DWC2_GPWRDN_MULTVALIDBC_RID_A_GND 12
548+
#define USB_DWC2_GPWRDN_MULTVALIDBC_RID_FLOAT 16
549+
#define USB_DWC2_GPWRDN_MULTVALIDBC_RID_C_FLOAT 17
550+
#define USB_DWC2_GPWRDN_MULTVALIDBC_RID_B_FLOAT 18
551+
#define USB_DWC2_GPWRDN_MULTVALIDBC_RID_1 31
552+
#define USB_DWC2_GPWRDN_BSESSVLD_POS 22UL
553+
#define USB_DWC2_GPWRDN_BSESSVLD BIT(USB_DWC2_GPWRDN_BSESSVLD_POS)
554+
#define USB_DWC2_GPWRDN_IDDIG_POS 21UL
555+
#define USB_DWC2_GPWRDN_IDDIG BIT(USB_DWC2_GPWRDN_IDDIG_POS)
556+
#define USB_DWC2_GPWRDN_LINESTATE_POS 19UL
557+
#define USB_DWC2_GPWRDN_LINESTATE_MASK (0x3UL << USB_DWC2_GPWRDN_LINESTATE_POS)
558+
#define USB_DWC2_GPWRDN_LINESTATE_DM0DP0 0
559+
#define USB_DWC2_GPWRDN_LINESTATE_DM0DP1 1
560+
#define USB_DWC2_GPWRDN_LINESTATE_DM1DP0 2
561+
#define USB_DWC2_GPWRDN_LINESTATE_NOT_DEFINED 3
562+
#define USB_DWC2_GPWRDN_STSCHNGINTMSK_POS 18UL
563+
#define USB_DWC2_GPWRDN_STSCHNGINTMSK BIT(USB_DWC2_GPWRDN_STSCHNGINTMSK_POS)
564+
#define USB_DWC2_GPWRDN_STSCHNGINT_POS 17UL
565+
#define USB_DWC2_GPWRDN_STSCHNGINT BIT(USB_DWC2_GPWRDN_STSCHNGINT_POS)
566+
#define USB_DWC2_GPWRDN_SRPDETECTMSK_POS 16UL
567+
#define USB_DWC2_GPWRDN_SRPDETECTMSK BIT(USB_DWC2_GPWRDN_SRPDETECTMSK_POS)
568+
#define USB_DWC2_GPWRDN_SRPDETECT_POS 15UL
569+
#define USB_DWC2_GPWRDN_SRPDETECT BIT(USB_DWC2_GPWRDN_SRPDETECT_POS)
570+
#define USB_DWC2_GPWRDN_CONNDETMSK_POS 14UL
571+
#define USB_DWC2_GPWRDN_CONNDETMSK BIT(USB_DWC2_GPWRDN_CONNDETMSK_POS)
572+
#define USB_DWC2_GPWRDN_CONNECTDET_POS 13UL
573+
#define USB_DWC2_GPWRDN_CONNECTDET BIT(USB_DWC2_GPWRDN_CONNECTDET_POS)
574+
#define USB_DWC2_GPWRDN_DISCONNECTDETECTMSK_POS 12UL
575+
#define USB_DWC2_GPWRDN_DISCONNECTDETECTMSK BIT(USB_DWC2_GPWRDN_DISCONNECTDETECTMSK_POS)
576+
#define USB_DWC2_GPWRDN_DISCONNECTDETECT_POS 11UL
577+
#define USB_DWC2_GPWRDN_DISCONNECTDETECT BIT(USB_DWC2_GPWRDN_DISCONNECTDETECT_POS)
578+
#define USB_DWC2_GPWRDN_RESETDETMSK_POS 10UL
579+
#define USB_DWC2_GPWRDN_RESETDETMSK BIT(USB_DWC2_GPWRDN_RESETDETMSK_POS)
580+
#define USB_DWC2_GPWRDN_RESETDETECTED_POS 9UL
581+
#define USB_DWC2_GPWRDN_RESETDETECTED BIT(USB_DWC2_GPWRDN_RESETDETECTED_POS)
582+
#define USB_DWC2_GPWRDN_LINESTAGECHANGEMSK_POS 8UL
583+
#define USB_DWC2_GPWRDN_LINESTAGECHANGEMSK BIT(USB_DWC2_GPWRDN_LINESTAGECHANGEMSK_POS)
584+
#define USB_DWC2_GPWRDN_LNSTSCHNG_POS 7UL
585+
#define USB_DWC2_GPWRDN_LNSTSCHNG BIT(USB_DWC2_GPWRDN_LNSTSCHNG_POS)
586+
#define USB_DWC2_GPWRDN_DISABLEVBUS_POS 6UL
587+
#define USB_DWC2_GPWRDN_DISABLEVBUS BIT(USB_DWC2_GPWRDN_DISABLEVBUS_POS)
588+
#define USB_DWC2_GPWRDN_PWRDNSWTCH_POS 5UL
589+
#define USB_DWC2_GPWRDN_PWRDNSWTCH BIT(USB_DWC2_GPWRDN_PWRDNSWTCH_POS)
590+
#define USB_DWC2_GPWRDN_PWRDNRST_N_POS 4UL
591+
#define USB_DWC2_GPWRDN_PWRDNRST_N BIT(USB_DWC2_GPWRDN_PWRDNRST_N_POS)
592+
#define USB_DWC2_GPWRDN_PWRDNCLMP_POS 3UL
593+
#define USB_DWC2_GPWRDN_PWRDNCLMP BIT(USB_DWC2_GPWRDN_PWRDNCLMP_POS)
594+
#define USB_DWC2_GPWRDN_RESTORE_POS 2UL
595+
#define USB_DWC2_GPWRDN_RESTORE BIT(USB_DWC2_GPWRDN_RESTORE_POS)
596+
#define USB_DWC2_GPWRDN_PMUACTV_POS 1UL
597+
#define USB_DWC2_GPWRDN_PMUACTV BIT(USB_DWC2_GPWRDN_PMUACTV_POS)
598+
#define USB_DWC2_GPWRDN_PMUINTSEL_POS 0UL
599+
#define USB_DWC2_GPWRDN_PMUINTSEL BIT(USB_DWC2_GPWRDN_PMUINTSEL_POS)
600+
601+
USB_DWC2_GET_FIELD_DEFINE(gpwrdn_multvalidbc, GPWRDN_MULTVALIDBC)
602+
USB_DWC2_GET_FIELD_DEFINE(gpwrdn_linestate, GPWRDN_LINESTATE)
603+
449604
/* GDFIFOCFG register */
450605
#define USB_DWC2_GDFIFOCFG 0x005CUL
451606
#define USB_DWC2_GDFIFOCFG_EPINFOBASEADDR_POS 16UL
@@ -805,6 +960,30 @@ USB_DWC2_GET_FIELD_DEFINE(doeptsizn_xfersize, DOEPTSIZN_XFERSIZE)
805960
USB_DWC2_SET_FIELD_DEFINE(doeptsizn_pktcnt, DOEPTSIZN_PKTCNT)
806961
USB_DWC2_SET_FIELD_DEFINE(doeptsizn_xfersize, DOEPTSIZN_XFERSIZE)
807962

963+
/* Power and Clock Gating Control Register */
964+
#define USB_DWC2_PCGCCTL 0x0E00UL
965+
#define USB_DWC2_PCGCCTL_RESTOREVALUE_POS 14UL
966+
#define USB_DWC2_PCGCCTL_RESTOREVALUE_MASK (0x3FFFFUL << USB_DWC2_PCGCCTL_RESTOREVALUE_POS)
967+
#define USB_DWC2_PCGCCTL_ESSREGRESTORED_POS 13UL
968+
#define USB_DWC2_PCGCCTL_ESSREGRESTORED BIT(USB_DWC2_PCGCCTL_ESSREGRESTORED_POS)
969+
#define USB_DWC2_PCGCCTL_RESTOREMODE_POS 9UL
970+
#define USB_DWC2_PCGCCTL_RESTOREMODE BIT(USB_DWC2_PCGCCTL_RESTOREMODE_POS)
971+
#define USB_DWC2_PCGCCTL_L1SUSPENDED_POS 7UL
972+
#define USB_DWC2_PCGCCTL_L1SUSPENDED BIT(USB_DWC2_PCGCCTL_L1SUSPENDED_POS)
973+
#define USB_DWC2_PCGCCTL_PHYSLEEP_POS 6UL
974+
#define USB_DWC2_PCGCCTL_PHYSLEEP BIT(USB_DWC2_PCGCCTL_PHYSLEEP_POS)
975+
#define USB_DWC2_PCGCCTL_ENBL_L1GATING_POS 5UL
976+
#define USB_DWC2_PCGCCTL_ENBL_L1GATING BIT(USB_DWC2_PCGCCTL_ENBL_L1GATING_POS)
977+
#define USB_DWC2_PCGCCTL_RSTPDWNMODULE_POS 3UL
978+
#define USB_DWC2_PCGCCTL_RSTPDWNMODULE BIT(USB_DWC2_PCGCCTL_RSTPDWNMODULE_POS)
979+
#define USB_DWC2_PCGCCTL_GATEHCLK_POS 1UL
980+
#define USB_DWC2_PCGCCTL_GATEHCLK BIT(USB_DWC2_PCGCCTL_GATEHCLK_POS)
981+
#define USB_DWC2_PCGCCTL_STOPPCLK_POS 0UL
982+
#define USB_DWC2_PCGCCTL_STOPPCLK BIT(USB_DWC2_PCGCCTL_STOPPCLK_POS)
983+
984+
USB_DWC2_GET_FIELD_DEFINE(pcgcctl_restorevalue, PCGCCTL_RESTOREVALUE)
985+
USB_DWC2_SET_FIELD_DEFINE(pcgcctl_restorevalue, PCGCCTL_RESTOREVALUE)
986+
808987
/*
809988
* Device IN/OUT endpoint transfer size register
810989
* IN at offsets 0x0910 + (0x20 * n), n = 0 .. x,

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