dts: st: stm32u5: restore correct clocks on multi-bit devices

During the transition to STM32_CLOCK macro (in 57723cf), the `clocks`
property of peripherals requiring more than one bit to be set were
mistakenly modified. Commit 2c3294b
partially fixed these errors, but some nodes for the U5 series are still
wrong.

Restore `clocks` on affected devices in corresponding STM32U5 DTSI.

Fixes: 57723cf
Signed-off-by: Mathieu Choplain <[email protected]>
(cherry picked from commit 37bdc38)

Author: Mathieu Choplain

dts/arm/st/u5/stm32u5.dtsi

@@ -304,7 +304,7 @@
 			compatible = "zephyr,memory-region", "st,stm32-backup-sram";
 			reg = <0x40036400 DT_SIZE_K(2)>;
 			/* BKPSRAMEN and RAMCFGEN clock enable */
-			clocks = <&rcc STM32_CLOCK(AHB1, 28U)>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 ((1 << 28) | (1 << 17))>;
 			zephyr,memory-region = "BACKUP_SRAM";
 			status = "disabled";
 		};

dts/arm/st/u5/stm32u595.dtsi

@@ -106,7 +106,8 @@
 			num-bidir-endpoints = <9>;
 			ram-size = <4096>;
 			maximum-speed = "high-speed";
-			clocks = <&rcc STM32_CLOCK(AHB2, 15U)>,
+			/* Enable OTG_HS PHY and peripheral clocks (OTGHSPHYEN | OTGEN) */
+			clocks = <&rcc STM32_CLOCK_BUS_AHB2 ((1 << 15) | (1 << 14))>,
 				 <&rcc STM32_SRC_HSI48 ICKLK_SEL(0)>;
 			phys = <&otghs_phy>;
 			status = "disabled";