Commit 44e3d05
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boards: st: stm32h7s78_dk: Add PLL2 node and SDMMC1 node
Configure SDMMC1 with 4-bit bus width and card detection. Use PLL2S
as kernel peripheral clock (150MHz) divided by 15 to achieve 10MHz
SDMMC clock with clk-div = <13>.
Signed-off-by: Shan Pen <[email protected]>1 parent ab5dce7 commit 44e3d05
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