soc: ti: add TI Hercules TMS570LC43x SoC

Adds new SoC. The vendor provides a tool (halcogen) to
generate code including SoC init and errata handling code, which
is also included here after adapting it to coding style and reducing
dependencies. As for erratas, the applicable one at this stage is PLL
startup errata.

We also have CORTEX-R5#7 (ARM ID-780125), but we did not implement it
due to several reasons:
1. did not implement it in the past codebase
2. Halcogen code does not implement it
3. This is Cortex R5 errata, Xilinx R5 implementation has this note
https://adaptivesupport.amd.com/s/article/65878

Signed-off-by: Tavish Naruka <[email protected]>

Author: Tavish Naruka

dts/arm/ti/tms570.dtsi

@@ -0,0 +1,71 @@
+/*
+* Copyright (c) 2025 ispace inc.
+*
+* SPDX-License-Identifier: Apache-2.0
+*/
+
+#include <mem.h>
+#include <arm/armv7-r.dtsi>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-r5";
+			reg = <0>;
+			status = "okay";
+		};
+	};
+
+	clocks {
+		/*
+		* OSC_IN (16 MHZ)
+		*  -> PLL1 (300 MHz)
+		*      -> GCLK1 (300 MHz)
+		*          -> HCLK (150 MHz)
+		*              -> VCLK (75 MHz)
+		*                  -> RTICLK (75 MHz, divider is bypassed when VCLK is the source)
+		*/
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		sys: sys@ffffff00 {
+			reg = <0xffffff00 256>,    /* SYS1 */
+			      <0xffffe100 256>,    /* SYS2 */
+			      <0xffff1000 0x800>,  /* PCR1 */
+			      <0xfcff1000 0x800>,  /* PCR2 */
+			      <0xfff78000 0x800>,  /* PCR3 */
+			      <0xfff87000 0x1000>, /* FCR  */
+			      <0xfffff500 0x100>,  /* ESM  */
+			      <0xFFFFFFE4 4>,	   /* SYS_EXCEPTION */
+			      <0xFFFFFC98 4>,	   /* WATCHDOG_STATUS */
+			      <0xFFFFEC00 44>;	   /* DCC */
+		};
+
+		sram0: memory@8000000 {
+			compatible = "mmio-sram";
+			reg = <0x08000000 DT_SIZE_K(512)>;
+		};
+
+		flc0: flash_controller@f0000000 {
+			compatible = "flash-controller";
+			reg = <0xf0000000 0x00480000>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+			status = "okay";
+
+			flash0: flash@0 {
+				compatible = "soc-nv-flash";
+				reg = <0x00000000 DT_SIZE_M(4)>;
+			};
+		};
+
+	};
+};

soc/ti/hercules/CMakeLists.txt

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(${SOC_NAME})
+
+zephyr_include_directories(${SOC_NAME})

soc/ti/hercules/Kconfig

@@ -0,0 +1,8 @@
+# Copyright (c) 2025 ispace, inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_FAMILY_HERCULES
+
+rsource "*/Kconfig"
+
+endif # SOC_FAMILY_HERCULES

soc/ti/hercules/Kconfig.defconfig

@@ -0,0 +1,8 @@
+# Copyright (c) 2025 ispace, inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_FAMILY_HERCULES
+
+rsource "*/Kconfig.defconfig"
+
+endif # SOC_FAMILY_HERCULES

soc/ti/hercules/Kconfig.soc

@@ -0,0 +1,10 @@
+# Copyright (c) 2025 ispace, inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_HERCULES
+	bool
+
+config SOC_FAMILY
+	default "ti_hercules" if SOC_FAMILY_HERCULES
+
+rsource "*/Kconfig.soc"

soc/ti/hercules/soc.yml

@@ -0,0 +1,2 @@
+socs:
+  - name: tms570lc43x

soc/ti/hercules/tms570lc43x/CMakeLists.txt

@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+# TMS470 requires the ARM "legacy Word Invariant Addressing big-endian mode"
+zephyr_compile_options(
+  -mbe32
+  ${TOOLCHAIN_C_FLAGS}
+)
+
+zephyr_ld_options(
+  -mbe32
+  ${TOOLCHAIN_LD_FLAGS}
+)
+
+zephyr_library_sources(
+  soc.c
+  soc_pll_errata.c
+  asm_funcs.S
+  )
+
+zephyr_library_include_directories(
+  ${ZEPHYR_BASE}/kernel/include
+  ${ZEPHYR_BASE}/arch/arm/include
+  )
+
+zephyr_include_directories(.)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_r/scripts/linker.ld CACHE INTERNAL "")

soc/ti/hercules/tms570lc43x/Kconfig

@@ -0,0 +1,21 @@
+# Copyright (c) 2025 ispace, inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_TI_TMS570LC43X
+	bool
+	select ARM
+	select CPU_CORTEX_R5
+	select BIG_ENDIAN
+	select CPU_HAS_DCLS
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_DCACHE
+	select CPU_HAS_ICACHE
+	select PLATFORM_SPECIFIC_INIT
+	select PLATFORM_SPECIFIC_PRE_STACK_INIT
+	# select CPU_HAS_FPU
+	# select ARM_CUSTOM_INTERRUPT_CONTROLLER
+	imply XIP
+
+if SOC_TI_TMS570LC43X
+
+endif # SOC_TI_TMS570LC43X

soc/ti/hercules/tms570lc43x/Kconfig.defconfig

@@ -0,0 +1,33 @@
+# Copyright (c) Copyright (c) 2025 ispace, inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_TI_TMS570LC43X
+
+config SYS_CLOCK_EXISTS
+	default n
+
+config MULTITHREADING
+	default n
+
+config GEN_SW_ISR_TABLE
+	default n
+
+config GEN_ISR_TABLES
+	default n
+
+# launchpad is 16MHz
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 16000000
+
+config FLASH_BASE_ADDRESS
+	default 1000000
+
+config FLASH_SIZE
+	default 4096
+
+config NUM_IRQS
+	int
+	# must be >= the highest interrupt number used
+	default 127
+
+endif # SOC_TI_TMS570LC43X

soc/ti/hercules/tms570lc43x/Kconfig.soc

@@ -0,0 +1,20 @@
+# Copyright (c) 2024 ispace, inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_TI_HERCULES
+	bool
+	select SOC_FAMILY_HERCULES
+	help
+	  TI Hercules family
+
+config SOC_TI_TMS570LC43X
+	bool
+	select SOC_SERIES_TI_HERCULES
+	help
+	  TI TMS570LC43X
+
+config SOC_SERIES
+	default "ti_hercules" if SOC_SERIES_TI_HERCULES
+
+config SOC
+	default "tms570lc43x" if SOC_TI_TMS570LC43X