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#define z_hsi_divider (v ) LL_RCC_HSI_DIV_ ## v
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#define hsi_divider (v ) z_hsi_divider(v)
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+ #if defined(LL_RCC_HCLK_DIV_1 )
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+ #define fn_ahb_prescaler (v ) LL_RCC_HCLK_DIV_ ## v
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+ #define ahb_prescaler (v ) fn_ahb_prescaler(v)
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+ #else
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#define fn_ahb_prescaler (v ) LL_RCC_SYSCLK_DIV_ ## v
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#define ahb_prescaler (v ) fn_ahb_prescaler(v)
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+ #endif
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#define fn_apb1_prescaler (v ) LL_RCC_APB1_DIV_ ## v
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#define apb1_prescaler (v ) fn_apb1_prescaler(v)
@@ -537,7 +542,7 @@ static void set_up_plls(void)
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*/
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if (LL_RCC_GetSysClkSource () == LL_RCC_SYS_CLKSOURCE_STATUS_PLL ) {
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stm32_clock_switch_to_hsi ();
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- LL_RCC_SetAHBPrescaler (LL_RCC_SYSCLK_DIV_1 );
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+ LL_RCC_SetAHBPrescaler (ahb_prescaler ( 1 ) );
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}
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LL_RCC_PLL_Disable ();
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@@ -800,9 +805,9 @@ int stm32_clock_control_init(const struct device *dev)
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set_up_plls ();
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if (DT_PROP (DT_NODELABEL (rcc ), undershoot_prevention ) &&
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- (STM32_CORE_PRESCALER == LL_RCC_SYSCLK_DIV_1 ) &&
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+ (ahb_prescaler ( STM32_CORE_PRESCALER ) == ahb_prescaler ( 1 ) ) &&
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(MHZ (80 ) < CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC )) {
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- LL_RCC_SetAHBPrescaler (LL_RCC_SYSCLK_DIV_2 );
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+ LL_RCC_SetAHBPrescaler (ahb_prescaler ( 2 ) );
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} else {
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LL_RCC_SetAHBPrescaler (ahb_prescaler (STM32_CORE_PRESCALER ));
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}
@@ -827,7 +832,7 @@ int stm32_clock_control_init(const struct device *dev)
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#endif /* STM32_SYSCLK_SRC_... */
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if (DT_PROP (DT_NODELABEL (rcc ), undershoot_prevention ) &&
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- (STM32_CORE_PRESCALER == LL_RCC_SYSCLK_DIV_1 ) &&
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+ (ahb_prescaler ( STM32_CORE_PRESCALER ) == ahb_prescaler ( 1 ) ) &&
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(MHZ (80 ) < CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC )) {
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LL_RCC_SetAHBPrescaler (ahb_prescaler (STM32_CORE_PRESCALER ));
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}
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