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#include <esp_cpu.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/drivers/entropy.h>
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- #if defined(SOC_RNG_CLOCK_IS_INDEPENDENT )
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#include <zephyr/drivers/clock_control.h>
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- #endif
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LOG_MODULE_REGISTER (entropy , CONFIG_ENTROPY_LOG_LEVEL );
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@@ -36,6 +34,9 @@ LOG_MODULE_REGISTER(entropy, CONFIG_ENTROPY_LOG_LEVEL);
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* plus additional overhead for the calculation, making it slower.
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*/
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#define APB_CYCLE_WAIT_NUM (160 * 16)
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+ #elif defined CONFIG_SOC_SERIES_ESP32H2
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+ /* Same reasoning as for ESP32C6, but the CPU frequency on ESP32H2 is 96MHz instead of 160 MHz */
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+ #define APB_CYCLE_WAIT_NUM (96 * 16)
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#else
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#define APB_CYCLE_WAIT_NUM (16)
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#endif
@@ -95,28 +96,17 @@ static int entropy_esp32_get_entropy(const struct device *dev, uint8_t *buf,
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static int entropy_esp32_init (const struct device * dev )
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{
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- int ret = 0 ;
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-
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- #if defined(SOC_RNG_CLOCK_IS_INDEPENDENT )
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- const struct device * clock_dev =
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- DEVICE_DT_GET (DT_CLOCKS_CTLR (DT_NODELABEL (trng0 )));
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+ const struct device * clock_dev = DEVICE_DT_GET (DT_CLOCKS_CTLR (DT_NODELABEL (trng0 )));
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clock_control_subsys_t clock_subsys =
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(clock_control_subsys_t )DT_CLOCKS_CELL (DT_NODELABEL (trng0 ), offset );
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if (!device_is_ready (clock_dev )) {
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return - ENODEV ;
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}
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- ret = clock_control_on (clock_dev , clock_subsys );
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+ clock_control_on (clock_dev , clock_subsys );
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- if (ret != 0 ) {
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- LOG_ERR ("Error enabling TRNG clock" );
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- }
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- #else
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- /* clock initialization handled by clock manager */
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- #endif
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-
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- return ret ;
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+ return 0 ;
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}
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static DEVICE_API (entropy , entropy_esp32_api_funcs ) = {
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