dts: arm: gigadevice: Add DMA configuration

Add DMA support for GD32 series.

Signed-off-by: TOKITA Hiroshi <[email protected]>

Author: soburi

dts/arm/gigadevice/gd32e10x/gd32e10x.dtsi

@@ -416,6 +416,28 @@
 			};
 		};
 
+		dma0: dma@40020000 {
+			compatible = "gd,gd32-dma";
+			reg = <0x40020000 0x400>;
+			interrupts = <11 0>, <12 0>, <13 0>, <14 0>,
+				     <15 0>, <16 0>, <17 0>;
+			rcu-periph-clock = <0x500>;
+			dma-channels = <7>;
+			#dma-cells = <1>;
+			status = "disabled";
+		};
+
+		dma1: dma@40020400 {
+			compatible = "gd,gd32-dma";
+			reg = <0x40020400 0x400>;
+			interrupts = <56 0>, <57 0>, <58 0>, <59 0>,
+				     <60 0>;
+			rcu-periph-clock = <0x501>;
+			dma-channels = <5>;
+			#dma-cells = <1>;
+			status = "disabled";
+		};
+
 	};
 };
 

dts/arm/gigadevice/gd32f3x0/gd32f3x0.dtsi

@@ -65,6 +65,16 @@
 			#io-channel-cells = <1>;
 		};
 
+		dma0: dma@40020000 {
+			compatible = "gd,gd32-dma";
+			reg = <0x40020000 0x400>;
+			interrupts = <9 0>, <10 0>, <11 0>, <48 0>;
+			rcu-periph-clock = <0x500>;
+			dma-channels = <7>;
+			#dma-cells = <1>;
+			status = "disabled";
+		};
+
 		pinctrl: pin-controller@48000000 {
 			compatible = "gd,gd32-pinctrl-af";
 			reg = <0x48000000 0x1800>;

dts/arm/gigadevice/gd32f403/gd32f403.dtsi

@@ -433,6 +433,28 @@
 				#pwm-cells = <3>;
 			};
 		};
+
+		dma0: dma@40020000 {
+			compatible = "gd,gd32-dma";
+			reg = <0x40026000 0x400>;
+			interrupts = <11 0>, <12 0>, <13 0>, <14 0>,
+				     <15 0>, <16 0>, <17 0>;
+			rcu-periph-clock = <0x500>;
+			dma-channels = <7>;
+			#dma-cells = <1>;
+			status = "disabled";
+		};
+
+		dma1: dma@40020400 {
+			compatible = "gd,gd32-dma";
+			reg = <0x40026400 0x400>;
+			interrupts = <56 0>, <57 0>, <58 0>, <59 0>,
+				     <60 0>;
+			rcu-periph-clock = <0x501>;
+			dma-channels = <5>;
+			#dma-cells = <1>;
+			status = "disabled";
+		};
 	};
 };
 

dts/arm/gigadevice/gd32f4xx/gd32f4xx.dtsi

@@ -554,6 +554,28 @@
 				#pwm-cells = <3>;
 			};
 		};
+
+		dma0: dma@40026000 {
+			compatible = "gd,gd32-dma";
+			reg = <0x40026000 0x400>;
+			interrupts = <11 0>, <12 0>, <13 0>, <14 0>,
+				     <15 0>, <16 0>, <17 0>, <47 0>;
+			rcu-periph-clock = <0xc15>;
+			dma-channels = <8>;
+			#dma-cells = <1>;
+			status = "disabled";
+		};
+
+		dma1: dma@40026400 {
+			compatible = "gd,gd32-dma";
+			reg = <0x40026400 0x400>;
+			interrupts = <56 0>, <57 0>, <58 0>, <59 0>,
+				     <60 0>, <68 0>, <69 0>, <70 0>;
+			rcu-periph-clock = <0xc16>;
+			dma-channels = <8>;
+			#dma-cells = <1>;
+			status = "disabled";
+		};
 	};
 };
 

dts/riscv/gigadevice/gd32vf103.dtsi

@@ -350,5 +350,29 @@
 			channels = <0>;
 			status = "disabled";
 		};
+
+		dma0: dma@40020000 {
+			compatible = "gd,gd32-dma";
+			reg = <0x40020000 0x400>;
+			interrupt-parent = <&eclic>;
+			interrupts = <30 0>, <31 0>, <32 0>, <33 0>,
+				     <34 0>, <35 0>, <36 0>;
+			rcu-periph-clock = <0x500>;
+			dma-channels = <7>;
+			#dma-cells = <1>;
+			status = "disabled";
+		};
+
+		dma1: dma@40020400 {
+			compatible = "gd,gd32-dma";
+			reg = <0x40020400 0x400>;
+			interrupt-parent = <&eclic>;
+			interrupts = <75 0>, <76 0>, <77 0>, <78 0>,
+				     <79 0>;
+			rcu-periph-clock = <0x501>;
+			dma-channels = <5>;
+			#dma-cells = <1>;
+			status = "disabled";
+		};
 	};
 };