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soc: renesas: Add support for Renesas RZ/A3M
Add support for Renesas RZ/A3M Signed-off-by: Nhut Nguyen <[email protected]>
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‎soc/renesas/rz/rza3m/CMakeLists.txt

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# Copyright (c) 2025 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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zephyr_sources(soc.c)
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zephyr_library_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c)
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zephyr_include_directories(.)
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zephyr_linker_sources(SECTIONS sections.ld)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "")

‎soc/renesas/rz/rza3m/Kconfig

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# Copyright (c) 2025 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_RZA3M
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select ARM64
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select CPU_CORTEX_A55
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select ARM_ARCH_TIMER
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select HAS_RENESAS_RZ_FSP
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select SOC_EARLY_INIT_HOOK

‎soc/renesas/rz/rza3m/Kconfig.defconfig

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# Copyright (c) 2025 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_RZA3M
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config SYS_CLOCK_EXISTS
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default y
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config NUM_IRQS
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default 512
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,/osc,clock-frequency)
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config FLASH_SIZE
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default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
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config FLASH_BASE_ADDRESS
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default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
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DT_CHOSEN_IMAGE_ZEPHYR = zephyr,code-partition
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DT_CHOSEN_SRAM_ZEPHYR = zephyr,sram
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config BUILD_OUTPUT_ADJUST_LMA
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default "$(dt_chosen_partition_addr_hex,$(DT_CHOSEN_IMAGE_ZEPHYR)) - \
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$(dt_chosen_reg_addr_hex,$(DT_CHOSEN_SRAM_ZEPHYR))"
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config BUILD_OUTPUT_ADJUST_LMA_SECTIONS
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default "*;!.header"
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endif # SOC_SERIES_RZA3M

‎soc/renesas/rz/rza3m/Kconfig.soc

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# Copyright (c) 2025 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_RZA3M
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bool
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select SOC_FAMILY_RENESAS_RZ
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help
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Renesas RZ/A3M series
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config SOC_SERIES
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default "rza3m" if SOC_SERIES_RZA3M
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config SOC_R9A07G066M04GBG
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bool
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select SOC_SERIES_RZA3M
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help
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R9A07G066M04GBG
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config SOC
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default "r9a07g066m04gbg" if SOC_R9A07G066M04GBG

‎soc/renesas/rz/rza3m/mmu_regions.c

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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/arch/arm64/arm_mmu.h>
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#include <zephyr/devicetree.h>
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static const struct arm_mmu_region mmu_regions[] = {
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MMU_REGION_FLAT_ENTRY("IO_REG", 0x10000000, 0x10000000,
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MT_DEVICE_nGnRnE | MT_RW | MT_DEFAULT_SECURE_STATE),
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};
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const struct arm_mmu_config mmu_config = {
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.num_regions = ARRAY_SIZE(mmu_regions),
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.mmu_regions = mmu_regions,
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};

‎soc/renesas/rz/rza3m/pinctrl_soc.h

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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SOC_RENESAS_RZ_RZA3M_PINCTRL_SOC_H_
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#define ZEPHYR_SOC_RENESAS_RZ_RZA3M_PINCTRL_SOC_H_
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#include <pinctrl_rza.h>
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#endif /* ZEPHYR_SOC_RENESAS_RZ_RZA3M_PINCTRL_SOC_H_ */

‎soc/renesas/rz/rza3m/sections.ld

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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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SECTION_PROLOGUE(.header, CONFIG_FLASH_BASE_ADDRESS,)
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{
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QUAD(__start)
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QUAD(0xFFFFFFFFFFFFFFFF-__start)
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QUAD(CONFIG_SRAM_BASE_ADDRESS)
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QUAD(0xFFFFFFFFFFFFFFFF-CONFIG_SRAM_BASE_ADDRESS)
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QUAD(z_mapped_size)
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QUAD(0xFFFFFFFFFFFFFFFF-z_mapped_size)
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FILL(0x00)
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. += 0x1B0;
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QUAD(0x4120505346205a52)
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QUAD(0x69746163696c7070)
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QUAD(0x0000000000006e6f)
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QUAD(0x0000000000000000)
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} > FLASH
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z_mapped_size = z_mapped_end - z_mapped_start;

‎soc/renesas/rz/rza3m/soc.c

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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for Renesas RZ/A3UL Group
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*/
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#include <zephyr/init.h>
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#include "soc.h"
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uint32_t SystemCoreClock;
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void soc_early_init_hook(void)
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{
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/* Configure system clocks. */
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bsp_clock_init();
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/* Initialize SystemCoreClock variable. */
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SystemCoreClockUpdate();
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}

‎soc/renesas/rz/rza3m/soc.h

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/*
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* Copyright (c) 2025 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SOC_RENESAS_RZA3M_SOC_H_
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#define ZEPHYR_SOC_RENESAS_RZA3M_SOC_H_
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#include <bsp_api.h>
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#endif /* ZEPHYR_SOC_RENESAS_RZA3M_SOC_H_ */

‎soc/renesas/rz/soc.yml

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- name: rza2m
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socs:
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- name: r7s921053vcbg
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- name: rza3m
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socs:
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- name: r9a07g066m04gbg
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- name: rza3ul
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socs:
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- name: r9a07g063u02gbg

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