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#include <soc.h>
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+ #if DT_ANY_INST_HAS_BOOL_STATUS_OKAY (rx_fifo_rx_we )
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+ #define USES_RX_FIFO_RX_WE 1
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+ #endif
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+
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+ BUILD_ASSERT (DT_ANY_INST_HAS_BOOL_STATUS_OKAY (rx_fifo_rx_we ) ==
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+ DT_ALL_INST_HAS_BOOL_STATUS_OKAY (rx_fifo_rx_we ),
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+ "rx-fifo-rx-we property must be set for all or none of the instances" );
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+
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#define UART_EV_TX BIT(0)
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#define UART_EV_RX BIT(1)
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@@ -73,11 +81,12 @@ static int uart_litex_poll_in(const struct device *dev, unsigned char *c)
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if (!litex_read8 (config -> rxempty_addr )) {
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* c = litex_read8 (config -> rxtx_addr );
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-
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+ #ifndef USES_RX_FIFO_RX_WE
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/* refresh UART_RXEMPTY by writing UART_EV_RX
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* to UART_EV_PENDING
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*/
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litex_write8 (UART_EV_RX , config -> ev_pending_addr );
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+ #endif
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return 0 ;
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}
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@@ -193,6 +202,12 @@ static int uart_litex_fifo_fill(const struct device *dev,
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litex_write8 (tx_data [i ], config -> rxtx_addr );
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}
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+ #ifndef USES_RX_FIFO_RX_WE
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+ /* LiteX uses EventSourceLevel for the UART since 22.09.2025,
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+ * where TX event is level triggered and pending is self-flushing,
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+ * so this is not needed anymore for new designs. When the dt property
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+ * rx-fifo-rx-we is set, we assume the design is new enough.
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+ */
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if (litex_read8 (config -> txfull_addr )) {
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/* only flush TX event if TX is really full */
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litex_write8 (UART_EV_TX , config -> ev_pending_addr );
@@ -202,6 +217,7 @@ static int uart_litex_fifo_fill(const struct device *dev,
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litex_write8 (0 , config -> rxtx_addr );
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}
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}
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+ #endif
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return i ;
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}
@@ -223,11 +239,12 @@ static int uart_litex_fifo_read(const struct device *dev,
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for (i = 0 ; i < size && !litex_read8 (config -> rxempty_addr ); i ++ ) {
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rx_data [i ] = litex_read8 (config -> rxtx_addr );
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-
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+ #ifndef USES_RX_FIFO_RX_WE
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/* refresh UART_RXEMPTY by writing UART_EV_RX
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* to UART_EV_PENDING
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*/
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litex_write8 (UART_EV_RX , config -> ev_pending_addr );
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+ #endif
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}
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return i ;
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