soc/mediatek/mtk_adsp: Always cache the full SRAM region

I think my original idea with this default MPU setup was that the top
bits of the (fast) SRAM region might be useful for host DMA that
needed better latencies than the (extremely slow) system DRAM
mappings.  So it should be left uncached for safety.

But unfortunately the author[1] of the SOF heap integration for this
platform decided to size the heap dynamically to use most of the SRAM
block (the vectors and a few other bits live at the bottom, but most
of .text is in DRAM).

Needless to say, an uncached heap is sort of a performance disaster.
It worked OK for default copy-only topologies but fell over the moment
we turned on nontrivial processing.

[1] Um... Hi.  Yeah, that's me too.

Signed-off-by: Andy Ross <[email protected]>

Author: andyross

soc/mediatek/mt8xxx/soc.c

@@ -197,7 +197,6 @@ static void enable_mpu(void)
 		{ 0x10000000, 0x06f00 },          /* MMIO registers */
 		{ 0x1d000000, 0x06000 },          /* inaccessible */
 		{ SRAM_START, 0xf7f00 },          /* cached SRAM */
-		{ (uint32_t)&_mtk_adsp_sram_end, 0x06f00 }, /* uncached SRAM */
 		{ SRAM_END,   0x06000 },          /* inaccessible */
 		{ DRAM_START, 0xf7f00 },          /* cached DRAM */
 		{ (uint32_t)&_mtk_adsp_dram_end, 0x06f00 }, /* uncached DRAM */