arch: riscv: isr.S: restore s0 before jumping to z_riscv_fatal_error_csf

Restore the s0 we saved early in ISR entry so it shows up
properly in the CSF.

Signed-off-by: David Reiss <[email protected]>
Signed-off-by: Yong Cong Sin <[email protected]>

Author: ycsin

arch/riscv/core/isr.S

@@ -443,6 +443,12 @@ do_fault:
 1:	mv a1, sp
 
 #ifdef CONFIG_EXCEPTION_DEBUG
+	/*
+	 * Restore the s0 we saved early in ISR entry
+	 * so it shows up properly in the CSF.
+	 */
+	lr s0, __struct_arch_esf_s0_OFFSET(sp)
+
 	/* Allocate space for caller-saved registers on current thread stack */
 	addi sp, sp, -__callee_saved_t_SIZEOF