soc: atmel: add base support for C2x SOC

Adds Atmel SAMC20 and SAMC21 soc. C series is based on Cortex-M0+.
C21 contains CAN interface.

The init routines are same for SAMC20 and SAMC21. They use one
clock OSC48M without configuration.

The code is inspirated from atmel_sam0/samd21.

Signed-off-by: Kamil Serwus <[email protected]>

Author: benys

drivers/flash/Kconfig.sam0

@@ -16,6 +16,8 @@ menuconfig SOC_FLASH_SAM0
 config SOC_FLASH_SAM0_EMULATE_BYTE_PAGES
 	bool "Emulate byte-sized pages"
 	depends on SOC_FLASH_SAM0
+	default y if SOC_SERIES_SAMC20 || \
+		     SOC_SERIES_SAMC21
 	help
 	  Emulate a device with byte-sized pages by doing a
 	  read/modify/erase/write.

dts/arm/atmel/samc20x15.dtsi

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2019 Gerson Fernando Budke
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <atmel/samc2x.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(4)>;
+	};
+
+	soc {
+		nvmctrl: nvmctrl@41004000  {
+			flash0: flash@0 {
+				reg = <0 DT_SIZE_K(32)>;
+			};
+		};
+	};
+};

dts/arm/atmel/samc20x16.dtsi

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2019 Gerson Fernando Budke
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <atmel/samc2x.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(8)>;
+	};
+
+	soc {
+		nvmctrl: nvmctrl@41004000  {
+			flash0: flash@0 {
+				reg = <0 DT_SIZE_K(64)>;
+			};
+		};
+	};
+};

dts/arm/atmel/samc20x17.dtsi

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2019 Gerson Fernando Budke
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <atmel/samc2x.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(16)>;
+	};
+
+	soc {
+		nvmctrl: nvmctrl@41004000  {
+			flash0: flash@0 {
+				reg = <0 DT_SIZE_K(128)>;
+			};
+		};
+	};
+};

dts/arm/atmel/samc20x18.dtsi

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2019 Gerson Fernando Budke
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <atmel/samc2x.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(32)>;
+	};
+
+	soc {
+		nvmctrl: nvmctrl@41004000  {
+			flash0: flash@0 {
+				reg = <0 DT_SIZE_K(256)>;
+			};
+		};
+	};
+};

dts/arm/atmel/samc21.dtsi

@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2022 Kamil Serwus
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+ #include <atmel/samc2x.dtsi>
+
+/ {
+	aliases {
+		sercom-4 = &sercom4;
+		sercom-5 = &sercom5;
+	};
+
+	soc {
+		adc1: adc@42004800 {
+			compatible = "atmel,sam0-adc";
+			status = "disabled";
+			reg = <0x42004800 0x30>;
+			interrupts = <26 0>;
+			interrupt-names = "resrdy";
+			clocks = <&gclk 34>, <&mclk 0x1c 18>;
+			clock-names = "GCLK", "MCLK";
+			gclk = <0>;
+			prescaler = <4>;
+			#io-channel-cells = <1>;
+		};
+
+		sercom4: sercom@42001400 {
+			compatible = "atmel,sam0-sercom";
+			reg = <0x42001400 0x40>;
+			interrupts = <13 0>;
+			clocks = <&gclk 23>, <&mclk 0x1c 5>;
+			clock-names = "GCLK", "MCLK";
+			status = "disabled";
+		};
+
+		sercom5: sercom@42001800 {
+			compatible = "atmel,sam0-sercom";
+			reg = <0x42001800 0x40>;
+			interrupts = <14 0>;
+			clocks = <&gclk 25>, <&mclk 0x1c 6>;
+			clock-names = "GCLK", "MCLK";
+			status = "disabled";
+		};
+	};
+};

dts/arm/atmel/samc21x15.dtsi

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2019 Gerson Fernando Budke
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <atmel/samc21.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(4)>;
+	};
+
+	soc {
+		nvmctrl: nvmctrl@41004000  {
+			flash0: flash@0 {
+				reg = <0 DT_SIZE_K(32)>;
+			};
+		};
+	};
+};

dts/arm/atmel/samc21x16.dtsi

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2019 Gerson Fernando Budke
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <atmel/samc21.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(8)>;
+	};
+
+	soc {
+		nvmctrl: nvmctrl@41004000  {
+			flash0: flash@0 {
+				reg = <0 DT_SIZE_K(64)>;
+			};
+		};
+	};
+};

dts/arm/atmel/samc21x17.dtsi

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2019 Gerson Fernando Budke
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <atmel/samc21.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(16)>;
+	};
+
+	soc {
+		nvmctrl: nvmctrl@41004000  {
+			flash0: flash@0 {
+				reg = <0 DT_SIZE_K(128)>;
+			};
+		};
+	};
+};

dts/arm/atmel/samc21x18.dtsi

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2019 Gerson Fernando Budke
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <atmel/samc21.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(32)>;
+	};
+
+	soc {
+		nvmctrl: nvmctrl@41004000  {
+			flash0: flash@0 {
+				reg = <0 DT_SIZE_K(256)>;
+			};
+		};
+	};
+};